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MicroZed Chronicles: Versal AI Edge and TE0950

In the 2024 MicroZed Chronicles, we are going to examine Versal in depth with a particular focus on the AI Edge series. We’ve looked at Versal in previous blogs

(1,2,3,4,5) but as the AI Edge range of devices and development boards become available, we are going to be focusing a lot on the boards because they bring the cost of entry down significantly.


To get started, we are going to be looking at the Trenz TE0950 development board which contains a Versal VE2302 engineering silicon version. This provides the developer with 34 AI Engine-ML, 464 DSP engines, 150K LUTS in the adaptable engines along with the dual-core Arm Cortex-A72 and R5 application processor and real-time processor units within the scalar engines.


If you are not familiar with the Versal AI Edge series, it is intended for edge-based applications, as its name states. Of course, edge-based applications are often power constrained and therefore the AI Edge range has been optimized not only for performance but also for power consumption.

To achieve this, there are some architectural changes compared to the AI Core series of devices. The most obvious, of course, is a reduced number of resources within the AI and Adaptable Engines. In the Adaptable Engines, this includes not only a reduced number of LUTs but also a reduced number of network-on-chip ports. The AI processing elements within the AI Engines are also different from those within the AI Core series. The AI Engine tiles used in the AI Edge series are AI Engine-ML tiles and not the same AI Engine tiles found in the AI Core devices. The major difference is AI Engine tiles support AI Vector extensions and also provide DSP Vector extensions enabling support for non-AI applications such as FFTs, filters and beamforming. The AI Engine-ML tiles, on the other hand, are optimized for AI applications with reduced support for DSP extensions.

There are of course other optimizations made across the AI Edge ranges, some of which are available depending on the device selected. One of the other large architectural differences is support for 40G Ethernet, not 100G.

Along with the Versal AI Edge device, the TE0950 provides developers with USB, SD, eMMC (32GB), 1G Ethernet and UART (via USB) from the MIO connected to the CIPS. Memory wise 4GB of DDR4 is provided along with 128 MB of QSPI for primary boot.

While the Adaptable Engines’ IO provides interfaces using CRUVI low and high speed connections, CSI-2, and FMC. The FMC is interesting because the Versal devices provide developers with two interface types connected to the Adaptable Engines: XPIO and HDIO.

XPIO is similar to HPIO which was provided on UltraScale+ devices and it supports voltage standards between 1.0V and 1.5V. It is exceptionally capable and we will do a deep dive in a later bog. To work with the FMC, however, we need to provide a wider voltage range support as such the TE0950 provides an Artix FPGA between the Versal VE2302 device and the FMC. This means if we want to use the FMC, we need to configure both the Versal and Artix devices. The Artix device is also connected to the zQSFP and the CRUVI-HS connectors.

HDIO is not available on all Versal devices but provides support for logic standards between 1.5V and 3.3V. On the TE0950, the bank 302 is the HDIO bank and provides 22 IO pins. This is connected to the CRUVI low speed connections and CSI-2 I2C and LED/switches.

I was so impressed with this board I thought I would record a little video about it.

Now that I have introduced the board, I will walk through how we can get a simple project up and running on it soon.

Workshops and Webinars

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include

Embedded System Book   Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here   Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.

Sponsored by AMD


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