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On-Demand Workshop
Digilent Arty Z7-20 Workshop

Format: On-demand Training Class 

Length: Session one: 60 Minutes

   Session two: 60 Minutes 

   Session Three: 60 Minutes

   Session Four: 60 Minutes 


This course was designed to use 

Vitis 2021.1 - Includes Vivado 

Petalinux 2021.1

Arty Z7-20 

Learn about Xilinx FPGA based around the Arty Z7-20. 

This workshop provides lectures and labs which shows how to get started with Xilinx FPGAs from hello world to embedded Linux.

Session 1

  1. Introduction to FPGA – What is constitutes a FPGA – LUT / FF etc – Benefits of programmable logic – special functions (DSP, PCIe BRAM etc) / Different types of FPGA OTP / Flash / SRAM – Xilinx is SRAM only but still good to know about others  

  2. Clocking  - What different types of clocking is provided in Xilinx FPGA – Clock Regions, Regional and Multi regional clocking, Clock Domain Crossing

  3. Interfacing  - Understanding programmable logic IO, IO standards , I/O SERDES. Delays etc, DDR3/4 considerations

  4. How do we program a FPGA – examining Design Capture / Simulation / Synthesis / Place and Root  / Bit File Generation – what occurs at each stage and the importance of it

  5. Constraints  - How do we use constraints for timing closure, clocking relationships, IO allocations, Placement in the Logic itself

  6. Xilinx Devices  - FPGA / SoC- inc RFSoC  / ACAP / Alveo  / SoM - what are they and what are the key differences – Where might customers use them ?

  7. Lab – Creating Vivado Designs / Simulation / Constraints and finding timing errors.

Session 2

  1. Processing In Xilinx Devices  - What are soft and hard core processors – Options for Xilinx Devices  - MicroBlaze, A9, A53, R5, A72 etc.  - Arm M1 / M3 and RISC-V – Pro and Cons of Hard vs Soft processors

  2. Multi-Processing in PS and PL – how we can do SIMD in both the PS (NEON) and PL (DSP48 etc)

  3. Multi Core Systems – Communication between the processors – OpenAMP – Mutex, Mail Boxes

  4. Arm eXtensible Interface  - How do we connect processing solutions with the programmable logic. Master and Slave Interfaces / AXI Networks effective transfer of data

  5. Debugging – integrated Logic Analyzer / System ILA / Cross Triggering (SoC Only)

  6. LAB  - Creating first FPGA design on Zynq A7 Board – walk through design capture / simulation / synthesis  / place and route / bit stream creation.

Session 3

  1. Embedded Linux – Xilinx PetaLinux – How do we create embedded Linux solutions

  2. PetaLinux Flow – how do we develop petalinux for our applications  - How does we configure for PL designs – Device Trees etc.

  3. Configuring PetaLinux for acceleration

  4. What is Open Cl and HLS concepts

  5. HLS Optimizations – How do we analyse and optimize HLS designs

  6. LAB  -Creation of MicroBlaze on the Arty Z7  Board – Creation of MB system – Introduces VITIS for the embedded Flow.

Session 4

  1. Rapid Prototyping with PYNQ – What is PYNQ and how can we work with it, what are the benefits for industrial clients – Why are some clients using it for rapid prototyping 

  2. Introduction to Machine Learning  - What are Neural Networks, What different types of networks  apply for Images vs Voice. Model Zoo’s,

  3. The Xilinx DPU – What is the DPU, how do we customize and configure it for our deployment needs

  4. Vitis – AI  what is it how do we use it to accelerate AI applications

  5. LAB  - Implementing math's in FPGA implementations.

Workshop Materials:

All Materials and Labs are provided on the Digilent website

© 2020 Adiuvo Engineering & Training, Ltd.

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