top of page

MicroZed Chronicles: Versal Address Map and DDR Memory Controller

In order to effectively architect solutions in Versal devices, we first need to understand how each of the elements within the device can communicate with each other.

This means we need to be able to understand the Versal global address map which provides 16 TB of address space and is based upon the Network on Chip (NoC). This global address map provides access and communication between all of the Versal architectural elements.


Such a large address space is segmented into several different regions which provide access to the processing system, CPM, DDR, PL access, and the AI engines.


The lower 4 GB of the address space contains the processing system and platform management controller registers. The first 2 GB of this address space is reserved for DDR memory access. The remaining 2 GB is split and provides system address space for the AXI PL LPD and FP interfaces, Octal SPI flash memory, and PCIe address region 0. The remaining 256 MB contains the configuration registers for the PS, PMC, and associated systems.


The entire address space can be visualized in the diagram below and the Versal technical manual (AM011) provides all the detailed information for the exact address locations.


The address space does, however, contain several points which we need to understand. The first of these is the PMC Alias. Several Versal devices contain stacked silicon interconnect, and as result, contain several PMCs. Each PMC has a NoC alias address which allows the optional PMCs to be addressed as necessary.


In our Versal applications, we may need a large data buffer off chip which is where the DDR memory system comes into play.


All Versal devices include at least one DDR Memory Controller (DDRMC) which is configured as part of the Network on Chip IP. Interfacing with the DDRMC are four NoC channels as shown in the address space. Each of these four NoC channels can have a different quality of service (QoS) applied, while the controller itself can be reconfigured as two separate units, both providing 32-bit DDR4 interfaces. Splitting the memory controller can aid performance.

The DDRMC provides the ability to perform read reordering. If you are not familiar with the practice of reordering, it is where the DDRMC will reorder transactions to improve memory access efficiency. The DDRMC in Versal has four states for the read back reordering.


Read Priority: Read transactions are given priority – default.


Write Priority: The number of write commands have exceeded a threshold and so writes will take priority until the pressure is lowered.


Write/Read: Efficient transactions are the priority in this state.


Starved: One or more read transactions are starved.


The DDRMC also supports a single error correcting double error detecting ECC. This is stored in an additional byte of memory (64-bits becomes 72, and 32-bits becomes 40). This allows single bit errors to be corrected on the fly and double bit errors to be reported.


When we are working with critical or high-reliability applications, we do not want single errors to evolve into double bit errors. To prevent this, background scrubbing is possible using the idle cycles of the controller. The scrubbing period for DDR4 can be set in the GUI versus being a fixed period for other supported memories.

Now that we understand more about the Versal address map and the NoC DDRMC, we can start taking a look at creating applications.


0 comments

Recent Posts

See All
bottom of page