AMD

Today is the last day of 2025, and it has been a remarkably busy one. At this time last year, I had no idea just how busy, but also how productive, this year would turn out to be. Let’s take a look at some numbers, and remember this is before including any client engineering work. 52 blogs , one technical blog written each week. Some of my favourites this year include Leveraging Performance , The FPGA Turns 40 , and Design Reuse . 21 Hackster projects , each exploring an FPGA

Over the twelve years of this blog, we have looked at many different tools for developing FPGA and SoC designs. Many we use often, such as Vivado, Vitis, and PetaLinux. Others, over the years, have been merged into or evolved into new products, for example SDSoC. One tool we have only touched on is Vitis Model Composer. This add-on for MATLAB and Simulink provides developers with a number of HDL and HLS blocks which can be connected to create FPGA solutions. Vitis Model Compo

One of the things I have been meaning to write about for a while now is an update to the Alinx Versal AI Edge 2302 VD100 development board project, which displayed a test pattern on an attached LCD display. The update to the project was to include an Alinx camera and create an image processing pipeline which enables live video to be captured by the camera and displayed on the LCD. Having the output pipeline already established, this is a relatively simple update to the design

One of the most talked-about areas in recent engineering workflows is the use of AI to generate code. I’ve explored this in the past , comparing Claude, Grok, and ChatGPT by asking them to create something simple such as a blinking LED. But as the models have matured, I wanted to revisit the topic and look at what has improved, especially now that agentic AI workflows are becoming practical. If you're unfamiliar with agentic AI, the key difference is that instead of only gene

FPGAs are great for implementing signal-processing functions such as FIR filters. The DSP elements, with their built-in multiply–accumulate capability, are ideally suited for this application. However, as with most things in FPGA design, the achievable performance depends heavily on how we architect the implementation. At a basic level, a FIR filter consists of three main elements: A delay line Multipliers to apply the coefficients An accumulator to sum the products Exactly h

One of the things I have been examining lately is how I can leverage higher-performing devices, such as the Spartan UltraScale+, to implement more compact FPGA designs. There are several approaches we can take to achieve this based on the higher performance of the logic. For example, we can run AXI buses narrower but at a higher frequency; in this case we leverage the increased performance of the fabric. This works well for interfaces around our module, although the core of t

I am always interested to see new tools and approaches being released into the FPGA world. Recently, I have been working a lot more with Versal devices for clients, in my blogs, and Hackster projects, especially the Versal Edge AI devices. With the Versal Edge AI, we have mostly examined the VE2302 device available on the Trenz TE950 or Alinx VD100 . We also recently looked at the VEK280 , which contains the VE2802, the largest of the Versal Edge AI devices. Of course, if we

I see a lot of designs across a range of industries and applications. One thing that always stands out is that designs often use complex state machines to implement features such as I²C, SPI, GPIO sequencing, etc. Often, these FSMs become unwieldy and complex, which adds to bring-up and debugging challenges. Of course, these FSMs also need to be verified in simulation and again on the board once they arrive. When I am asked to work with these interfaces in an FPGA, I often re

I’ve been meaning to take a closer look at our new Spartan-7 Tile Rev B and the Tile Carrier Card for a while now. They’ve been sitting on my lab bench while I’ve been wrapping up work from recent conferences and client projects, so this week, I finally found the time. The Spartan-7 Tile Rev B  is an evolution of the original Rev A design. It includes a revised boot-mode selection switch in place of a jumper and features a slightly different pinout to support discrete JTAG. T

Recently, I’ve noticed a lot of questions on social media and Reddit/FPGA about setting up your own engineering company. Having run one for about 15 years now, I thought I’d hold a webinar on running your own business. The webinar was one of the most enjoyable I’ve done in a while. You can see the full webinar here , but I thought it might be a good idea to share some key takeaways from the session in this blog. Being highly technical and competent on its own is not enough .

Long-time readers of this blog will know that I am a huge fan of the PYNQ framework. We have used PYNQ in several blogs and Hackster projects, most recently in one that used a LIDAR to help control the safety of a robotic arm as it operated in its environment. PYNQ has also featured heavily in our webinars over the years. I was therefore very excited to discover a few weeks ago that version 3.1 of PYNQ had been released. This is the first release of PYNQ since version 3.0 in

Over the past few months, we’ve explored several Versal™ AI Edge development boards, including the Trenz TE0905 and the Alinx Txxxx. Each of these boards is built around the VE2303 device, which provides 330K system logic cells, 464 DSP engines, 34 AI Engine-ML tiles, and 5 NoC ports. For a recent AI development project, however, I needed something with significantly more capability. That led me to the VEK280, which features the largest device in the Versal AI Edge family. It

Back in February, I announced the first dedicated FPGA conference, to be held in London on October 7th. Once we had settled on a name,...

Recently we have been developing numerous boards based around AMD devices from our Spartan 7 and RPI2040 based embedded system board, to...

FPGAs are great, they allow us to process data at rates unachievable by any other means. However, this comes with a challenge: we need to...

Recently, I’ve been looking at a project that uses Aurora to transfer data over fibre as fast as possible from one FPGA to another. The...

Over the last few months I have been doing a lot of work with Versal devices and the AI Engines provided on devices like the XCV2302 and...

Recently, I have been doing a lot of work with the SCU35 and the Spartan UltraScale+ FPGA it features. Much of this work revolves around...

One project we have in the pipeline involves the need to transfer data from one FPGA to another over a fibre link with minimal delay....

I am a regular contributor to many FPGA channels. A few days ago, someone posted a question about what FPGA consultants actually do. The...