AMD

FPGA Conference - FPGA Horizons US East - April 29th, 30th 2026 - THE FPGA Conference, find out more and get Tickets here . Recently, we have looked at how we can use AI in our RTL development and in our software development within Vitis . AMD is also going to be running a very interesting tutorial on upcoming AI features within FPGA at FPGA Horizons US . This got me thinking that I should write a little more about how I am using it and the flow I am using in my developments

One of the recurring themes across many of my blogs and projects is the development of image processing solutions. Typically, these solutions are output to a display—most often HDMI, and occasionally DisplayPort. DisplayPort is particularly useful for MPSoC-based image processing applications because it is integrated within the Processing System (PS) of the device and outputs via the PS GTR transceivers. Using the PS DisplayPort, we can generate graphics from DDR memory, outp

Over the last few weeks and months I have found myself working on several Versal designs. One of the most important aspects of working with Versal devices is having a verification strategy. Versal devices are impressive with the combination of the CIPS, AIE and PL, to get the best from the device our solution often uses a combination of these diverse processing elements. While working on these projects I have also been exploring the verification capabilities available within

One of the things I have been meaning to write about for some time is how we provided flexible interfacing when we developed the Tile Carrier Card. Of course, we wanted the Embedded System Tile to be able to communicate with both the Raspberry Pi Compute Module and the Pmod interfaces available on the board. Pmods provide support for a wide range of interface standards, from common protocols such as SPI, I²C, and UART through to higher-speed interfaces like TMDS for DVI and R

One of the most commonly implemented FPGA features is clock division. When dividing clocks there are several possible approaches depending upon the application. For simple integer division we can use counters implemented in logic, while more complex requirements such as frequency multiplication or fractional division typically require a PLL or MMCM. Previously we explored clock division in 7-series devices using the BUFGCE, and in UltraScale devices using the BUFGCE_DIV. Thes

One thing that is very useful for many applications is the GEMs within the PS of the MPSoC. We can use these to provide simple networking and communication, or alternatively as part of a larger application. Recently, I was thinking about the performance that can be achieved. For this application, I decided to set up a design which uses the GEM and the PS to parse packets as they are received and route the packets into one of two BRAMs within the PL. The GEM is capable of oper

Sometimes I like to just sit and write RTL and try to create a simple project. Recently, I have been doing a lot of flying again. If you see me on a flight, you can be sure you are in for a turbulent experience, as it seems every flight I take is bumpy (sorry!). For a long while, I have been meaning to run a small experiment and create a compact, portable logging system which records acceleration, rotation, pressure, and temperature. I decided that I could do this using a sma

This is one of the boards I have been waiting to get my hands on for a long time: the Tria VE2302 development kit. This is the development kit for the Tria VE2302 SoM and provides developers with four 22-pin MIPI CSI / DSI connectors, two zSFP connectors, HDMI Tx and Rx, along with Gigabit Ethernet and USB 2.0 ports. There is also a TXR2 interface which is capable of being operated with some SYZYGY / ZMod boards, as we will see in future blogs. The board also provides USB UAR

Over the last few months, it has become apparent that DRAM is increasing in price and becoming harder to source. This is especially true in the consumer market, driven in part by increased demand from AI workloads. We tend to think of using the latest generation, which currently means DDR5 or LPDDR5. DDR5 has some interesting architectural changes, which enable increased bandwidth, much faster transfer rates, and higher device densities. For example, DDR5 DIMMs are effectivel

Some of my most interesting professional developments have involved using high-sampling-rate ADCs and DACs with FPGAs. The FPGA is a natural partner for communications, RADAR, and electronic warfare (EW) systems, all of which rely on ADCs and DACs operating at giga-samples per second (GSPS). The RFSoC range combines giga-sample ADCs and DACs with high-performance programmable logic and processor engines. First introduced in 2018, we have examined RFSoC devices, particularly t

The Spartan UltraScale+ is a very interesting device. Not only does the UltraScale+ fabric enable us to leverage performance to implement more functionality in a smaller device, for example see my recent FPGA Horizons  journal article on logic folding , but it also offers a wide range of powerful built-in features. It is not just the capability of the logic that makes the Spartan UltraScale+ so useful. It is also the many integrated features, including its enhanced security c

We have recently looked at using AI when we develop RTL solutions using Copilot in VS Code. However, many of the applications I work on include a MicroBlaze V, or are Zynq, Zynq MPSoC or Versal based. As such, I also need to develop software-based solutions. As such, it would be good to be able to accelerate our embedded software development using AI frameworks. However, before we look at the integration of AI frameworks within Vitis, I want to talk about the Eclipse framewor

Over the last 12 months, it seems we have developed several FPGA-based boards, both as Adiuvo products and for clients. We have also been pulled into supporting FPGAs on boards that clients have designed. Often these client-designed boards have been developed on time-constrained schedules, and hence they are hoping for the best. So I am going to start off the new year talking about how we are able to reduce the technical risk in our board designs. The first thing to consider

Today is the last day of 2025, and it has been a remarkably busy one. At this time last year, I had no idea just how busy, but also how productive, this year would turn out to be. Let’s take a look at some numbers, and remember this is before including any client engineering work. 52 blogs , one technical blog written each week. Some of my favourites this year include Leveraging Performance , The FPGA Turns 40 , and Design Reuse . 21 Hackster projects , each exploring an FPGA

Over the twelve years of this blog, we have looked at many different tools for developing FPGA and SoC designs. Many we use often, such as Vivado, Vitis, and PetaLinux. Others, over the years, have been merged into or evolved into new products, for example SDSoC. One tool we have only touched on is Vitis Model Composer. This add-on for MATLAB and Simulink provides developers with a number of HDL and HLS blocks which can be connected to create FPGA solutions. Vitis Model Compo

One of the things I have been meaning to write about for a while now is an update to the Alinx Versal AI Edge 2302 VD100 development board project, which displayed a test pattern on an attached LCD display. The update to the project was to include an Alinx camera and create an image processing pipeline which enables live video to be captured by the camera and displayed on the LCD. Having the output pipeline already established, this is a relatively simple update to the design

One of the most talked-about areas in recent engineering workflows is the use of AI to generate code. I’ve explored this in the past , comparing Claude, Grok, and ChatGPT by asking them to create something simple such as a blinking LED. But as the models have matured, I wanted to revisit the topic and look at what has improved, especially now that agentic AI workflows are becoming practical. If you're unfamiliar with agentic AI, the key difference is that instead of only gene

FPGAs are great for implementing signal-processing functions such as FIR filters. The DSP elements, with their built-in multiply–accumulate capability, are ideally suited for this application. However, as with most things in FPGA design, the achievable performance depends heavily on how we architect the implementation. At a basic level, a FIR filter consists of three main elements: A delay line Multipliers to apply the coefficients An accumulator to sum the products Exactly h

One of the things I have been examining lately is how I can leverage higher-performing devices, such as the Spartan UltraScale+, to implement more compact FPGA designs. There are several approaches we can take to achieve this based on the higher performance of the logic. For example, we can run AXI buses narrower but at a higher frequency; in this case we leverage the increased performance of the fabric. This works well for interfaces around our module, although the core of t

I am always interested to see new tools and approaches being released into the FPGA world. Recently, I have been working a lot more with Versal devices for clients, in my blogs, and Hackster projects, especially the Versal Edge AI devices. With the Versal Edge AI, we have mostly examined the VE2302 device available on the Trenz TE950 or Alinx VD100 . We also recently looked at the VEK280 , which contains the VE2802, the largest of the Versal Edge AI devices. Of course, if we