All About HLS
Format: On-demand webinar (recorded from previous live event)
Length: 70 Minutes
Developing FPGA IP using RTL such as VHDL or Verilog is great however the development and verification time can be considerable. In this session we are going to examine how High Level Synthesis can be used to accelerate algorithm development.
In this session we are going to look at
Topics covered in this tutorial:
What is HLS – How does it work.
HLS Flow – What is the flow of development from C/C++ to bitstream in Vivado / Vitis.
Why HLS – Where is it beneficial to use HLS and where is it not
Algorithm development / debugging and verification
Acceleration Libraries - Vitis accelerated libraries & leveraging these
Rules of HLS development / coding – What rules do we need to consider when developing HLS solutions
Optimizing code for performance – Finding parallelism and bottlenecks, managing performance vs resources while optimizing for performance
Interfacing – Controlling interfaces in HLS to implement the most appropriate interface for our solution
Worked example – A detailed walk through of a HLS solution
Download the lab book and slides here.
There are no Prerequisites
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