A couple of weeks ago I started exploring, fixed and floating point math and the differences between them in FPGA implementations. Of...

When it comes to debugging designs the more visibility and control we have over debugging elements such as ILAs is critical.   When we...

One of the nice things about writing this blog is that I get to take a look at many new FPGA and SoC boards. A few weeks ago, I received...

One of the pivotal architectural enhancements in the Versal family of devices was the introduction of the Network on Chip. Within the...

A couple of weeks ago we looked at the Trenz TE0950 development board which contains a Versal AI Edge XCVE2302 device in ES1. This means...

In the 2024 MicroZed Chronicles, we are going to examine Versal in depth with a particular focus on the AI Edge series. We’ve looked at...

Over the last few weeks, we have looked at some interesting aspects of the 7 series and UltraScale / UltraScale+ clocking buffers. To...

We looked at fixed point math a few weeks ago and we’ve also previously looked at how we can use DSP48 in both 7 series and UltraScale+...

In order to effectively architect solutions in Versal devices, we first need to understand how each of the elements within the device can...

In the first instalment of this Versal miniseries, I briefly introduced the architecture of the Versal devices before showing a simple...