top of page

MicroZed Chronicles: Custom K26 Kria Board Design and Bring Up

One of the projects we’ve been working on recently is the development of a custom K26 carrier board. This project is interesting because it’s intended to prototype using a K26 SOM in place of a MicroZed SOM currently in the deployed their industrial system. The use of the K26 would reduce the number of MicroZeds required because there is more IO available in the overall system.

As such, we designed a simple interposer board which takes a K26 SOM and provides the necessary power and logic level conversion as well as implements Ethernet, USB, and FTDI JTAG  / UART. This design also includes a boot mode switch and SD Card cage to enable the K26 SOM to boot from the SD Card.


While your technical risk is significantly reduced by using a SOM like the K26, we still need to carefully consider the requirements of the project. The only way to do this professionally is to start out with a definition of the problem that the carrier card is trying to address and then set clearly defined requirements. These requirements inform the basis of the design process and enable us to then create an architecture. Initially, this architecture will consist of high-level block diagrams. However, as the design progresses and engineers read data sheets, user guides, and application notes, it’s possible to create a detailed architecture which provides both the key elements of the design and also the internally and externally required interfaces.


We have to work with the K26 and make sure we include all of the interfaces the SOM requires to function. Of course, we can understand a little about the SOM and its interfaces from the data sheet but AMD also provides three very useful documents to help us on this journey:



When it comes to doing the layout, we might also need to consider the net length reports on the SOM traces so we can match them on our carrier card. You can find the K26 net length report here XTP688


Note that there is a slight delay between the completion of the board design and the arrival of the first testable prototypes. We can take this time before the board arrives to work out a test plan which defines the tests and test equipment needed to bring up the board.


Since the K26 is a SoC and the majority of the interfaces on this carrier card are connected to the PS, the initial design for bring up will be focused on the PS side.


Before we can progress to testing the initial functionality, we need to check that the K26 powers up safely in the carrier card. Here, I checked the status of the 5 Volt SOM power along with the power management signals from the carrier to the module (C2M) to ensure they were as expected. These signals can power down the SOM (PWROFF_C2M_L) and reset the SOM PS_POR_L and PS_SRST_C2M_L. Once satisfied that the carrier was safe to mate with the K26 SOM, the next stage is to mate the SOM and power on the board.


With the SOM connected and power applied as expected, the SOM will power up enabling the SOM’s power good signals to be verified. For this board, we also added LEDs on the M2C power good status signals.

Once we know the power is good, the next step in the bring up is to try and detect the K26 Zynq UltraScale+ MPSoC over JTAG.


Since we used a FTDI chip and the circuits provided by AMD on the K26 carrier card schematics, we can program the FTDI device using hardware manager to implement the JTAG functionality.


program_ftdi -write -ftdi FT4232H -serial AD2401 -vendor "Adiuvo" -board "<name>" -desc "<customer>"

Once the programming of the FTDI has been completed, we will see the K26 device appear in device manager. This means we can now program the device and run designs on the PS and the PL. As I said, the first idea stage is to test the UART, SD Card and I2C network.


The simple Vivado block design is shown below with the GEM, USB, UART, and SD Card MIO correctly configured for the carrier card design. The mode pins on the carrier card were set to boot from the SD Card and a simple BareMetal hello world program was generated in Vitis along with the boot.bin.


Copying the boot.bin to a SD card and powering the design will result in the BareMetal application booting successfully and the output being shown on a terminal window.

I also recorded the current consumption while the board was booted using an energy monitor. The K26 requires about 5W during the boot and initial operation phase. At this point, I have not done anything to optimize for power efficiency and this also includes all of the convertor losses on the carrier card.

With the SD Card and terminal shown as working, the next step was to create a PetaLinux image. This image is pretty simple and uses a RAM-based FS. The only customization made to the file system is the inclusion of the I2C tools.


By using the I2C tools, we are able to detect the devices on the I2C network. This should be a mix of devices on the SOM and carrier card.

From this we can observe the following devices:


Addresses 0x30, 0x32, 0x33 relate to PMICs on the SoM while 0x50 and 0x58 relate to the SOM EEPROM. Finally addresses 0x68 and 0x70 are the PL and PS current monitors on the SOM.


Contained on the carrier card, the clock generator is present at address 0x6A and the EEPROM at address 0x51 and 0x59.


This means that we are able to see and configure the clock generator which is what is needed for the USB and Ethernet clocks. While these can be programmed on the fly into volatile memory, these will be lost after a power cycle. As a result, we need to use a programming adaptor to program the NVRAM within the clock generator to ensure the device powers up with the clocks output at the correct frequencies.


So far this looks pretty good. Once the clock programmer arrives, I am sure the Ethernet and USB will function as intended thereby allowing me to progress to application testing which resides in the PL.

Workshops and Webinars

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include

Embedded System Book   

Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here   Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.

Sponsored by AMD


bottom of page