MicroZed Chronicles: Hello World from Versal and Vitis
A few weeks ago, I was lucky enough to receive a VMK180 development board. This board contains the Versal ACAP Prime VM1802 device along with a range of interfacing solutions from FMC to Ethernet QSFP and SFP. Memory wise, it also has 8GB DDR4 DIMM and 8GB of LPDDR4 which is more than enough to demonstrate many applications.
As I begin to discuss Versal ACAPs in my blogs more, we will take a deeper look at the device architecture and the tool flow in both Vivado and Vitis. For the first blog, however, it seemed sensible to do a quick walk through of how to get a bare metal program up and running so that we can say the traditional “hello world.” Most of the flow itself is very straight forward, however, we will need to learn a lot of new acronyms.
For the walk through to make sense, we need to understand a little about the architecture of the device. For the VM1802, the internals of the device can be defined as the following:
Processor System (PS) – This contains the dual-core A72 (APU) and the R5F (RPU) real-time processors.
Platform Management Controller (PMC) – This contains two TMR MicroBlaze instantiations and addresses control the boot, configuration of the PL, and the overall platform.
Network-on-Chip (NoC) – This is the network on chip that provides high-speed communication across the device.
Cache Coherent Interconnect (CCIX) for Accelerators and PCIe (CPM) – As the primary PCIe interface for the PS, it also allows accelerators in the PL to connect to the CCIX and act as a CCIX accelerator.
To get started creating a simple “hello world” application, we first need to create a device image in Vivado.
Once a project has been created for the VMK180 development board, the next step is to create a block diagram where we can add the configuration of the processing system, PMC, and the network-on-chip.
To get a simple system up and running we need to configure the PMC, PS, and NoC. We need to configure the NoC as the DDR controller is connected to the NoC. This means we need to configure the NoC and connect it to the processing system and PMC to run our software application from the attached DDR memory.
Once the block diagram has been created, the next step is to add the CIPS block onto the diagram. CIPS is the control, interfaces, and processing system. It is within the CIPS block that we configure the MIO, the boot mode, NoC, PS/PL interfaces, clocking, and the CPM configuration. With the CIPS block added, the next step is to run the block automation and configure the CIPS module for the VMK180.
When the block automation is run, the first step is to ensure we enable a memory controller under the options. We can leave all of the other options unchanged.
Double clicking to recustomize the CIPS module will present us with a number of configuration options. Ensure the IP interface for the PS is set to CIPS FIXED IO on the board tab. This will configure the PMC MIO and PS MIO for the board.
Clicking on the home tab will show a schematic of the different power domains and available internal and external interfaces. Notice we have a range of NoC and traditional AXI interconnects for internal connections.
Under the PS-PMC tab, you will be able to see the configuration for all of the CIPS IO. I must say that compared to the Zynq-7000 SoC / Zynq MPSoC presentation of the MIO, I really prefer this presentation style.
If we want to observe the configuration for a specific pin, we can click on the List view to see more details about each of the pins and their settings. Note that here I am checking that PMC MIO pin 37 is a GPIO output to address an answer record on the VMK180 board that I am working with.
The final element of the design in the CIPS block is in the configuration of the NoC. Ensure that all the PS Master coherent and non coherent interfaces are enabled.
The final configuration of the NoC is on the Advanced tab that enables the coherency for the USB, GEM, and LPDMA channels. If the Advanced tab is not shown, check that the CIPS config parameter PMC_SHOW_CCI_SMMU_SETTINGS in the CIP properties is set to true.
With the CIPS block complete, we need to configure the NoC module because we now have eight NoC interfaces from the CIPS module that need to be connected to the NoC.
Double click on the NoC to recustomize it. On the Board tab, select the DDR4 DIM for the CH0_DDR4_0 and the sys_clk0 should be set to DDR4 dimm1 sma clk.
On the General tab, select the number of NoC AXI Slave interfaces as 8, along with the same number of clocks.
Once the input tab is set, the AXI interfaces are connected as shown in the diagram below.
Finally, we need to set the clock frequency to 200 MHz on the DDR General tab.
The design is now complete and can be seen in the diagram below. Change the Sys_CLK input frequency to 200 MHz also.
Validate the design and generate the device image, note the device image for Versal devices is a programmable device image (PDI). This contains significantly more information than a standard BIT file previously used.
Once the PDI is available, we can export an XSA from Vivado and get started generating our own application software.
The flow is pretty much identical to the development flow we have previously used for Zynq-7000, Zynq MPSoC, Zynq RFSoC, and MicroBlaze developments.
To get started, we will create an application that uses the XSA we just exported from Vivado as the platform. When it’s time to create a new project, you will see the many different processors available within the processor system.
Follow through with the wizard and create a new “hello world” application.
Once the project is created, build both the platform and the application before launching a debugging session on the VMK180. Ensure the Boot mode is set to JTAG and run the debugger. With a terminal connected, you will see the output from the “hello world” application.
This has been a fast introduction to the Versal flow but a good one to pipe clean the development tool flow. Over the coming weeks and months, I will be doing more Versal ACAP blogs intermixed with all the other blogs, to take a closer look at the device and how to create applications.