Over the last few weeks, we have looked at some interesting aspects of the 7 series and UltraScale / UltraScale+ clocking buffers. To finish our short examination of clocking, I am going to look at Versal and its clocking capabilities in this blog. We are definitely beginning to see more and more interest in Versal design solutions.
Let’s start at the beginning. With Versal there are two IO standards available. The first is high-performance XP I/O (XPIO) which supports high-performance interface standards with voltage ranges between 1v0 and 1v5. While the second is high-density HD I/O (HDIO).which supports interface standards between 1v8 and 3v3. XPIO and HDIO, therefore, support different IO standards with no overlap (this is slightly different to UltraScale IO resources).
When it comes to clocking Versal devices, we need to use a differential clock source which connects to Global Clock (GC) pin pairs. Each XPIO bank provides four GC pairs, while each HDIO bank provides two pin pairs.
Internally, the Versal architecture provides developers with a range of advanced clocking resources which include:
Mixed Mode Clock Manager (MMCM) – this is the main element used for frequency synthesis, jitter filtering, and clock de-skewing.
All Digital PLL (DPLL) – DPPL are located in HDIO and GT clocking columns and are collocated with MMCMs. The DPLL has some limitation in capabilities compared to what can be achieved with a MMCM or XPLL.
XPLL – Primarily used for frequency synthesis and jitter filtering. The XPLL is primarily intended for use with the XPHY and memory interface logic IP
Along with the MMCM, DPLL and XPLL within the Versal device, we find clocking structures and buffers.
When it comes to clocking structure, the Versal architecture is divided into a several clock regions (CR). Within each CR, we find resources such as CLBs, DSP, and BRAMs. The exact mix may vary across clock regions but it will always be the same vertically in the device. To distribute clocks across our clocking regions, there are 12 horizontal and 24 horizontal routing tracks and 24 vertical distribution and routing tracks. Clock routing lines are provided to enable the routing of the clock from a buffer to the clock root where it is distributed to the loads.
Versal provides several clock buffers types to work with the GC inputs, DPLL, XPLL and MMCM as well as distribute the clocks across our devices. These include:
BUFGCTRL – Provides clock muxing and gating
BGFGCE – Enables clock gating
BUFGCE_DIV – Enables clock division
BUFG_GT – Support GT clocks
BUFG_PS – Provide access to the PL clock routing from the PS clocks
The functionality of these buffers is closely aligned with previous families. If we are familiar with working with those, we should be able to start in Versal pretty quickly.
Overall, the clocking resources in Versal provide us with the necessary element which we can use to build our example on top of.
The next step is to take a look at the Versal Network on Chip.
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