Over the last few weeks, we have been working to create a simple system which allows debugging from a UART into an AXI Lite network. This can be used for commissioning and board bring up. We have created the following elements on this journey so far:
UART to AXI Stream interface – External communication is over a UART Tx/Rx pins and internal FPGA communications uses AXI Stream.
AXI Protocol – Receives commands, addresses, and data over AXI Streaming interfaces before performing appropriate AXI Lite transaction.
Since these two modules are connected by AXI Streams for the final test, we can implement the custom UART and AXI protocol block in a Vivado project with an AXI Bram Controller and BRAM.
This will enable us to use a cocotb test bench to verify that the system works as expected. Once we are happy with the simulation behavior, the next step is the to try it on hardware.
I created a new Vivado project to get started. We can target any AMD development board like the Ultra96-V2 I selected for this example.
Once the project is created, we need to add in the UART and AXI protocol files previously created. With these added to the project, we can then add them onto a new blank IP integrator block diagram.
To complete the IP integrator design, the next stage is to add in an AXI BRAM Controller and a BRAM. With all the components present in the design, they can be connected as shown below.
We will be connecting to the TX and RX pins using the cocotb UART extensions within the cocotb environment to enable the injection of commands and receive the data on reads.
Using this method, we can enter commands to read and write over the AXI network. If this works correctly, we should be able to write in a word and then read it back from the Block RAM.
At the heart of cocotb simulations is the make file. In the make file for this simulation we need to ensure we have included not only the protocol and UART files but also the generated files by Vivado. These generated files include a wrapper for each module in the design including the UART and protocol block. We also need to add in to the source files for the AXI BRAM Controller and BRAM and each of these will provide simulation models that can be used.
The protocol entered over the UART is fairly simple and is recapped below.
With a structure as below
Write Op Code – 1 Byte, Value 0x09
Read Op Code – 1 Byte, Value 0x05
Address – 4 Bytes the address of the AXI interaction
Length – 1 Byte always 1 for AXI Lite implementations
Payload – Words to be write or received data, 4 Bytes are provided for an AXI Lite read or write
Running this in the simulation environment shows the commands being received over the UART and being passed on to the protocol block for action.
Reception of AXI write command over UART and write
AXI write in more detail.
Reception of AXI read command over UART and read
AXI read
I will write this up in more detail as a step-by-step Hackster project in the next few days to provide a detailed tutorial.
Workshops and Webinars
Enjoy the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and Petalinux
Arty Z7-20 Class looking at HW, SW and Petalinux
Mastering MicroBlaze learn how to create MicroBlaze solutions
HLS Hero Workshop learn how to create High Level Synthesis based solutions
Embedded System Book
Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design.
We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here
Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.
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