MicroZed Chronicles: 2025 What a Year!

Today is the last day of 2025, and it has been a remarkably busy one. At this time last year, I had no idea just how busy, but also how productive, this year would turn out to be.

Let’s take a look at some numbers, and remember this is before including any client engineering work.

• 52 blogs, one technical blog written each week. Some of my favourites this year include Leveraging Performance, The FPGA Turns 40, and Design Reuse.

• 21 Hackster projects, each exploring an FPGA or SoC development in depth, including 4K imaging at 60 Hz on Artix UltraScale+ and System Design with Vitis Unified.

• 10 conferences attended and spoken at, including SEFUW, EDHPC, PCB East / West, and FPGA World, with keynote presentations at two of them.

• Four white papers written, covering topics from robotics to AIE for DSP.

• Four training courses delivered on FPGA design and mission critical design.

• Four webinars hosted on working with FPGAs and starting your own business.

• Two new FPGA based products added.

• One conference launched, FPGA Horizons, the inaugural FPGA conference in the UK, with over 290 attendees and 28 exhibitors. Selected talks, including the keynote, are available on the FPGA Horizons YouTube channel.

• One journal launched, the FPGA Horizons Journal, published quarterly. Inspired by the Xilinx Xcell Journal that started me on this path, it focuses on evergreen FPGA design content. The first issue includes articles on clock domain crossing, FPGA verification, 100G UDP on Versal, along with in depth pieces on signal integrity and FPGA vs SoM strategies for PCB layout.

When it comes to client projects, we have designed and delivered Kria carrier cards, developed image processing systems for armoured vehicles, helped clients identify and resolve legacy design issues, and created innovative projects targeting Versal and Alveo platforms.

I also invested in new test equipment this year. My investment of the year has been the Exostiv probe, which enables SERDES links to be used for debugging FPGA designs in a way similar to an ILA, but in real time and with streaming capability.

I have some big plans to demonstrate how this can be applied to image processing applications in 2026.

One particularly interesting trend to watch is the impact of AI. It is increasingly being integrated into development tools to help users work more effectively, as well as being used in more agentic approaches to generate FPGA solutions. I have even heard that someone has been training an AI on all 600 plus issues of MicroZed Chronicles.

You could say it has been a rather busy year.

Looking ahead, 2026 looks even more exciting. We will have the first full year of the FPGA Horizons Journal, along with two conferences planned, one in April 2026 in the US and another in October in the UK. I will also be attending several conferences, including CERN’s FPGA Developers Forum.

What have you been working on with FPGAs in 2025, and what are your goals for 2026? I am very curious to hear. Are there any areas or topics you would like me to focus on next year? I tend to identify topics organically as I see what might be interesting and valuable to explore.

FPGA Conference

FPGA Horizons US East - April 28th, 29th 2026 - THE FPGA Conference, find out more here.

FPGA Journal

Read about cutting edge FPGA developments, in the FPGA Horizons Journal or contribute an article.

Workshops and Webinars:

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include:

• Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal

• Professional PYNQ Learn how to use PYNQ in your developments

• Introduction to Vivado learn how to use AMD Vivado

• Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux

• Arty Z7-20 Class looking at HW, SW and PetaLinux

• Mastering MicroBlaze  learn how to create MicroBlaze solutions

• HLS Hero Workshop  learn how to create High Level Synthesis based solutions

• Perfecting Petalinux  learn how to create and work with PetaLinux OS

Boards

Get an Adiuvo development board:

• Adiuvo Embedded System Development board - Embedded System Development Board

• Adiuvo Embedded System Tile - Low Risk way to add a FPGA to your design.

• SpaceWire CODEC - SpaceWire CODEC, digital download, AXIS Interfaces

• SpaceWire RMAP Initiator - SpaceWire RMAP Initiator,  digital download, AXIS & AXI4 Interfaces

• SpaceWire RMAP Target - SpaceWire Target, digital download, AXI4 and AXIS Interfaces

• Other Adiuvo Boards & Projects.

Embedded System Book   

Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here.  Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.

Sponsored by AMD