We regularly hold live OnDemand webinars & workshops. Here are some we made earlier…
Webinars & workshops
Webinars
Introduction to Vivado
The foundation of all AMD FPGA and SoC designs is Vivado ML Edition software. Vivado enables us to create and implement designs for our FPGA and SoC, along with creating platforms which can be built upon using accelerated flows for SoC applications.
120 minutes
This introductory session to Vivado will teach developers how to work effectively and confidently, covering topics such as:
-
Vivado overview – its role in the development process and where it fits with AMD FPGA toolchains
-
Project creation modes - GUI, command line (Project and Non-Project flow)
-
Working with IP Integrator
-
Creating and working with custom IP
-
Synthesis and implementation flow - including design checkpoints and out-of-context synthesis
-
Timing analysis - how do we find and correct issues in the implementation
-
Design assessment and risk reduction using design analysis report and quality of result suggestions
-
Clock Domain Crossing
-
Workshop materials
Download the lab book and slides here
Prerequisites
None
Lights, Lens, logic
Unlock the Power of Embedded Vision: FPGA Solutions from Sensor to Screen.
Whether you’re new to vision systems or looking to sharpen your FPGA expertise, this session will equip you with practical insights and real-world examples you can apply immediately.
60 minutes
-
How do image sensors actually work?
-
Get to grips with the core principles behind image sensors and understand the magic that turns photons into digital data.
-
Sensor Types Demystified
-
CIS vs CCD, rolling vs global shutter, colour vs greyscale — we’ll break down the differences and help you choose the right sensor for your application.
-
Connecting the Dots: Interfacing with Sensors & Cameras
-
From hardware interfaces to internal FPGA connections, learn how to bridge the gap between your vision input and your processing pipeline.
-
Inside the FPGA: Architecture & IP Blocks
-
Discover how to move, buffer, and manipulate pixels. We’ll explore key concepts like frame buffering, colour space conversion, and image filters — and show how to build them into scalable FPGA designs.
-
Hands-On Example: Real FPGA Vision Solution
-
We’ll wrap up with a deep technical dive into a real-world embedded vision pipeline, powered by the AMD Kintex™ 7 FPGA. See how it all comes together in practice.
All examples will be presented using AMD Vivado™ Design Suite version 2024.1.
-
Workshop materials
Download the lab book and slides here
Prerequisites
None
AMD Vivado™ Design Suite Essentials: Key Techniques for Superior RTL Development
How we architect and develop our programmable logic can have a large impact on how our designs perform and the time taken to achieve a workable solution.
This webinar will examine how we can architect and develop our programmable logic to ensure a successful outcome.
60 minutes
-
The importance of correct architecting
-
Simple rules to apply when creating an architecture
-
Decomposition of architecture - how do we split into manageable modules
-
How to leverage standard interfaces and existing IP blocks
-
Design reuse
-
Working with control sets
-
Pipelining
-
When and how to pipeline
-
Pipelining approaches and strategies
-
Auto-pipelining
-
Workshop materials
Download the lab book and slides here
Prerequisites
None
Tackling Timing
One of the most challenging areas in logic design is creating the correct timing constraints.
Get it wrong, and not only does your design not achieve the desired performance, but the implementation time may also take longer.
This webinar will examine not only how to define timing constraints which we can use for our AMD FPGAs but also how to investigate and correct timing errors (should they occur).
60 minutes
-
What is timing closure?
-
What is its objective?
-
What does timing success look like in AMD devices?
-
Challenges and impacts on projects presented by timing closure
-
Clocks and clocking resources in programmable logic
-
What are constraints?
-
Clock Domain Crossing
-
Timing closure approach
-
Analyzing timing closure violations
-
Leveraging of reports
-
Example walk through of a project failing timing closure, identifying and addressing issues
All examples will be presented using AMD Vivado™ Design Suite 2024.1
-
Workshop materials
Download the lab book and slides here
Prerequisites
None
From Chaos to Clarity: CDC Methodologies for Success
Modern FPGA designs contain multiple synchronous and asynchronous clock domains.
Transferring data between these clock domains comes with its own challenges, get it wrong and it can be many hours in the lab, or worse the field trying to determine the root cause.
This webinar is aimed at enabling engineers to be able to understand the challenges which come with designing in a multi-clock environment, and provide the knowledge to be successful in that environment.
60 minutes
-
How are clocks related - What makes a clock domain synchronous or asynchronous
-
What is Clock Domain Crossing - How can it impact out designs
-
CDC considerations - Is it just internal or do we need to consider IO as well
-
CDC Structures - Synchronisers, FIFO, Pulse, XPM and Open Source Libraries e.g. Open Logic
-
Special Types of CDC - Reset Domain Crossing / Synchronous CDC
-
Methods to find CDC in our Design - Why using STA and simulation is challenging.
-
Informing our selected design tool about clock relationships - constraints.
-
Finding CDC in designs using Blue Pearl Visual Verification Suite.
This webinar is intended to provide the attendee with a good introduction to CDC, along with understanding of the approaches and mitigation to take during design and implementation to make their design successful.
The webinar is presented in association with Blue Pearl Software and includes demonstrations of the Visual Verification Suite.
-
Prerequisites
None
Magical Maths
Programmable logic is used across a wide range of applications, from signal and image processing to robotics and machine learning.
At the core of these applications is the ability to implement mathematical algorithms within a programmable logic.
This webinar provides an introduction and thorough grounding on how mathematical algorithms can be implemented in programmable logic.
There is an emphasis on how we can leverage the features provided by AMD programmable logic to implement these algorithms to provide the best performance.
60 minutes
-
Introduction to applications using maths in programmable logic
-
The difference between fixed and floating point maths
-
Why programmable logic is often more suited to fixed point maths
-
How do we work with fixed point maths in programmable logic
-
What are the rules of fixed point maths in programmable logic?
-
How we can implement complex algorithms and filters using fixed point maths
-
The benefits of using AMD Vitis™ High Level Synthesis to implement algorithms
-
Leveraging Matlab / Simulink and AMD Vitis™ Model Composer to implement math solutions.
All examples will be presented using AMD Vivado™ Design Suite 2024.1.
-
Workshop materials
Download the lab book and slides here
Prerequisites
None
Mixed Signal Madness
The world is best processed digitally by much of the information within it is analog. This webinar is going to examine how we can work with devices from the AMD Cost Optimized Portfolio in a mixed signal environment.
This webinar focuses on leveraging the XADC / Sysmon and generating analog waveforms using digital IO (e.g. Delta Sigma DAC).
60 minutes
-
Mixed signal applications
-
ADC and DAC basics
-
Nyquist and the rules of sampling a signal
-
Aliasing signals
-
Working with the XADC / Sysmon with external sensors
-
An XADC example application in the real world
-
Creating a Delta Sigma DAC
-
Creating a PWM DAC
This session leverages many of the techniques presented in our Magical Maths webinar (see above).
All examples will be presented using AMD Vivado™ Design Suite 2024.1.
-
Workshop materials
Download the lab book and slides here
Prerequisites
None
AMD Cost Optimised Portfolio
5 minutes 57
-
Mixed signal applications
-
ADC and DAC basics
-
Nyquist and the rules of sampling a signal
-
Aliasing signals
-
Working with the XADC / Sysmon with external sensors
-
An XADC example application in the real world
-
Creating a Delta Sigma DAC
-
Creating a PWM DAC
This session leverages many of the techniques presented in our Magical Maths webinar (see above).
All examples will be presented using AMD Vivado™ Design Suite 2024.1.
-
Workshop materials
Download the lab book and slides here
Prerequisites
None
Mastering MicroBlaze
Learn how to develop MicroBlaze solutions from scratch for your AMD-Xilinx Device. In this webinar we take a tour through the MicroBlaze architecture, interfaces, configuration, use cases and deployment.
It's followed by a in depth live lab and build of a MicroBlaze System on the SP701 Board.
120 minutes
-
Why do we need sequential processing in a parallel world?
-
Overview of MicroBlaze variants
-
MicroBlaze architecture
-
Working with memories and caches
-
Interfacing with peripherals
-
Clock and interrupts
-
Operating systems - Bare Metal / FreeRTOS / Petalinux
-
Multi-processor communication – Communication between MicroBlaze
-
Boot and configuration of MicroBlaze
-
Networked communications
-
Detailed Lab, showing step by step implementation
-
Workshop materials
Download the lab book and slides here
Prerequisites
-
A Xilinx Spartan-7 FPGA SP701 Board will be used as the primary example in this workshop, but Digilent Arty-A7 or Arty-S7 boards are also suitable options
-
AMD-Xilinx Vitis 2021.2 or later
-
Mastering the AMD MicroBlaze™ Processor: The PetaLinux Class
120 minutes
-
Creating an AMD MicroBlaze processor design in AMD Vivado™ software – Necessary configurations of the AMD MicroBlaze processor and additional logic components required (e.g. Timer, SPI, Ethernet Lite etc.)
-
How to create a PetaLinux project
-
An introduction to the AMD device tree and how to customize the device tree to work with I2C-Dev and SPI-Dev.
-
How to customize the PetaLinux kernel to support User SPI Access
-
How to customize the PetaLinux kernel to support I2C tools
-
How to build and package PetaLinux
-
How to program and download PetaLinux for development
-
How to create applications and debug using the AMD Vitis™ software
Target Development board: Digilent Arty A7.
Development Tools: AMD Vivado™ 2023.2, AMD Vitis™ 2023.2 and PetaLinux 2023.2.
AMD and the AMD Arrow logo, MicroBlaze, Vitis, Vivado and combinations thereof are trademarks of Advanced Micro Devices Inc.
-
Workshop materials
Download the lab book and slides here
Prerequisites
-
To build along you will need a Linux Machine or a Linux Virtual Machine. Please see the steps here to create the Virtual Machine.
-
Perfecting Petalinux Workshop
Do you want to use PetaLinux Embedded Linux solutions on your AMD Xilinx processor?
AMD Xilinx devices such as the Zynq-7000, Zynq UltraScale+ MPSoC, Versal and MicroBlaze provide us with a range of processing solutions which can be used for our embedded systems.
Many applications require the use of an embedded Linux solution. Within the AMD Xilinx ecosystem this is often provided by using PetaLinux.
This workshop helps attendees get started with PetaLinux.
120 minutes
-
What is PetaLinux - Why do we use it and when
-
The PetaLinux project flow - How does it integrate with Vitis and Vivado
-
PetaLinux and Yocto
-
Understanding the PetaLinux boot flow
-
Device trees
-
Customizing device trees for applications
-
Project creation - Importing hardware designs
-
Customizing Kernel / Root FS
-
Creating SW applications
-
Debugging applications
-
Workshop materials
Download the lab book and slides here
Prerequisites
None
Professional PYNQ
Created by the AMD University Team for its academic program PYNQ fuses the productivity of python with the performance of the programmable logic available within the Zynq and MPSoC.
This workshop introduces the PYNQ framework and demonstrate the applicability of PYNQ for a range of uses in a professional environment, from accelerating prototyping of algorithms to providing PYNQ enabled test systems.
As a hands on workshop, this workshop walks attendees through several applications along with showing attendees how to create custom PYNQ overlays using Vivado.
120 minutes
-
What is PYNQ
-
How PYNQ can benefit your project
-
The PYNQ Framework – Overlays, IP and Drivers
-
Working with PYNQ and Jupyter
-
Libraries
-
Registers Maps
-
MicroBlaze in PYNQ Ecosystem
-
Advanced PYNQ – Compossible overlays and Partial Reconfiguration
-
Outline of the PYNQ overlay creation process – Including key rules and considerations
-
Hands on creation of PYNQ applications demonstrating the ease of creating and testing algorithms with PYNQ
-
Workshop materials
Download the lab book and slides here
Prerequisites
-
Supported PYNQ board:
http://www.pynq.io/board.html -
Vivado 2022.2:
https://www.xilinx.com/support/download.html -
PYNQ image on SD Card (Available at the same PYNQ.io link as above)
-
Building Accelerated Applications with Vitis
The Vitis Unified Software Platform enables developers to more easily tap into the benefits of Xilinx heterogeneous SoCs and accelerate their applications, without needing advanced hardware development knowledge. In this recorded workshop we walk through an in-depth tutorial on how to get started with Vitis and Vitis AI.
Timestamps:
00:00:00 - Vitis, OpenCL, Optimization Techniques
00:48:00 - Lab One
01:02:00 - Software Emulation for Lab One
01:07:00 - Hardware Emulation for Lab One
01:12:00 - Hardware Emulation - Vivado Simulation Integration
01:17:00 - Vitis Analyzer
01:21:00 - Vitis HLS integration
01:26:00 - Lab Two
01:28:00 - Cloning Vitis-AI
01:38:00 - Create DPU Xilinx Object
01:41:00 - Importing DPU Xilinx Object to Vitis
01:44:00 - Open pre implemented project - to show DPU integration
01:45:00 - Vivado Integration
01:50:00 - Wrap up and Questions
120 minutes
-
Vitis features and elements
-
Vitis libraries
-
OpenCL
-
Vitis development flows
-
Optimizing software for programmable logic implementation
-
Vitis AI for machine learning inference acceleration
-
…and more!
-
Workshop materials
Download the lab book and slides here
Prerequisites
To follow the exercises in this on-demand workshop, you will need to download and install Vitis 2020.1. Here's how...>
Vitis HLS Hero Workshop
High-Level Synthesis allows us to take our C++ / C models and high-level Vitis libraries to accelerate the development our programmable logic solution. In this workshop, we will walk through several design examples while introducing key points of developing an HLS Solution.
120 minutes
-
Create sources and test benches
-
Debug applications when it does not go as expected
-
How to control the interfaces presented to the Vivado design on the final IP block
-
Understand the default optimisations made by synthesis
-
How to identify bottlenecks in the design and select constraints to optimize the design and achieve the desired performance
-
How to leverage the arbitrary precision capabilities of Vitis to implement mathematical algorithms
-
How to leverage the wider world of Vitis HLS libraries so users no longer have create commonly used functions from scratch
-
Workshop materials
Download the lab book and slides here
Prerequisites
None
All About HLS
Developing FPGA IP using RTL such as VHDL or Verilog is great. However the development and verification time can be considerable. In this session we are going to examine how High Level Synthesis can be used to accelerate algorithm development.
70 minutes
-
What is HLS – How does it work.
-
HLS Flow – What is the flow of development from C/C++ to bitstream in Vivado / Vitis.
-
Why HLS – Where is it beneficial to use HLS and where is it not
-
Algorithm development / debugging and verification
-
Acceleration Libraries - Vitis accelerated libraries & leveraging these
-
Rules of HLS development / coding – What rules do we need to consider when developing HLS solutions
-
Optimizing code for performance – Finding parallelism and bottlenecks, managing performance vs resources while optimizing for performance
-
Interfacing – Controlling interfaces in HLS to implement the most appropriate interface for our solution
-
Worked example – A detailed walk through of a HLS solution
-
Workshop materials
Download the lab book and slides here
Prerequisites
None
Navigating Nios V
NIOS-V is the RISC-V Implementation for Intel FPGAs replacing the extremely popular NIOS-2.
In this workshop we are going to not only take a look at the NIOS-V but also examine the development tools and work through step by step how to create a simple NIOS V solutions.
To enable attendees to follow along Intel will be making available trial licenses for the Quartus Prime.
60 minutes
-
What is NIOS V
-
Which devices are currently supported and role out plan
-
Examine the basic architecture of NIOS-V Clocks, Reset, Address Space, Debug
-
Development overview – Tool chains / EcoSystem
-
HW Tool Chain Quartus Prime / Platform Designer
-
SW Tool chain RiscFree IDE for Intel FPGA
-
Workshop materials
Download the lab book and slides here
Prerequisites
Quartus Prime and Nios V Software licences can be obtained from the Intel Self Service License Center
Edge Impulse - Agricultural Robot
Edge Impulse is a cloud based TinyML framework which enables developers to capture data, create ML networks, train the network and deploy the resultant network on microcontrollers.
In this recorded workshop we walk through an project targeting the Sony Spresense development board to identify different crop types for a robotic agricultural application.
30 minutes
-
What is edge impulse
-
Obtaining the Data Set
-
Creating a Edge Impulse Project
-
Tagging and organizing the data
-
Creating the impulse
-
Improving the Results
-
Classification in the cloud to test the impulse
-
Deploying the code on the Sony Spresense
-
Workshop materials
Download the lab book and slides here
Prerequisites
You will need a Edge Impulse account. Accounts are free to create and use for Developers.
Mission Critical Workshop
When faced with environmental challenges such as extreme temperatures, electrical noise, shock, vibration and even radiation, incorrectly designed systems can fail. System failure can not only impact a company's reputation, but have far worse consequences such as injury, loss of life or environmental damage in the case of mission-critical systems.
In this webinar we will explore the different kinds of challenges embedded systems can face, what end effects these challenges have on embedded systems and how we mitigate these impacts in our designs. Understanding the challenges and mitigating them correctly ensures our designs are robust and safe.
60 minutes
-
Challenges faced by embedded systems and how these impact our systems
-
How failures manifest, systematic / random faults, avoidance and tolerance, common causes and fault propagation
-
Governance and standards (e.g., IEC61508, DO-254)
-
Design analysis techniques such as part stress, FMECA and structural code analysis
-
Design mitigation techniques such as high-reliability state machines, triple modular redundancy and communications schemes
-
Workshop materials
Download the lab book and slides here
Prerequisites
None
Basys 3 Pong Workshop
Learn how to build an FPGA-based embedded system while creating a fun, modern Pong/Breakout-like game. In this workshop, we'll cover everything you need to know about the Xilinx Ecosystem to get up and running, while exploring all the capabilities of the awesome Digilent Basys3 board.
Each session is 60 minutes
Workshops
Digilent Arty Z7-20 Workshop
Learn about Xilinx FPGA based around the Arty Z7-20.
This workshop provides lectures and labs which shows how to get started with Xilinx FPGAs from hello world to embedded Linux.
Each session is 60 minutes
Workshop materials
All Materials and Labs are provided on the Digilent website
Prerequisites
This course was designed to use:
Vitis 2021.1 - Includes Vivado
Petalinux 2021.1
Arty Z7-20
Session 4
-
Rapid Prototyping with PYNQ – What is PYNQ and how can we work with it, what are the benefits for industrial clients – Why are some clients using it for rapid prototyping
-
Introduction to Machine Learning - What are Neural Networks, What different types of networks apply for Images vs Voice. Model Zoo’s,
-
The Xilinx DPU – What is the DPU, how do we customize and configure it for our deployment needs
-
Vitis AI – What is it and how do we use it to accelerate AI applications
-
LAB - Implementing math's in FPGA implementations.
Session 3
-
Embedded Linux – Xilinx PetaLinux – How do we create embedded Linux solutions
-
PetaLinux Flow – how do we develop petalinux for our applications - How does we configure for PL designs – Device Trees etc.
-
Configuring PetaLinux for acceleration
-
What is Open Cl and HLS concepts
-
HLS Optimizations – How do we analyse and optimize HLS designs
-
LAB -Creation of MicroBlaze on the Arty Z7 Board – Creation of MB system – Introduces VITIS for the embedded Flow.
Session 2
-
Processing In Xilinx Devices - What are soft and hard core processors – Options for Xilinx Devices - MicroBlaze, A9, A53, R5, A72 etc. - Arm M1 / M3 and RISC-V – Pro and Cons of Hard vs Soft processors
-
Multi-Processing in PS and PL – how we can do SIMD in both the PS (NEON) and PL (DSP48 etc)
-
Multi Core Systems – Communication between the processors – OpenAMP – Mutex, Mail Boxes
-
Arm eXtensible Interface - How do we connect processing solutions with the programmable logic. Master and Slave Interfaces / AXI Networks effective transfer of data
-
Debugging – integrated Logic Analyzer / System ILA / Cross Triggering (SoC Only)
-
LAB - Creating first FPGA design on Zynq A7 Board – walk through design capture / simulation / synthesis / place and route / bit stream creation.
Session 1
-
Introduction to FPGA – What is constitutes a FPGA – LUT / FF etc – Benefits of programmable logic – special functions (DSP, PCIe BRAM etc) / Different types of FPGA OTP / Flash / SRAM – Xilinx is SRAM only but still good to know about others
-
Clocking - What different types of clocking is provided in Xilinx FPGA – Clock Regions, Regional and Multi regional clocking, Clock Domain Crossing
-
Interfacing - Understanding programmable logic IO, IO standards , I/O SERDES. Delays etc, DDR3/4 considerations
-
How do we program a FPGA – examining Design Capture / Simulation / Synthesis / Place and Root / Bit File Generation – what occurs at each stage and the importance of it
-
Constraints - How do we use constraints for timing closure, clocking relationships, IO allocations, Placement in the Logic itself
-
Xilinx Devices - FPGA / SoC- inc RFSoC / ACAP / Alveo / SoM - what are they and what are the key differences – Where might customers use them ?
-
Lab – Creating Vivado Designs / Simulation / Constraints and finding timing errors.