What attendees have said
The FPGA training course I did online was very well presented by Adam Taylor and followed a logical progression that was easy to understand. Adam was more than willing to answer questions. The exercises were at a good level, and also followed a logical process.
I learned a lot during the course and would recommend the course to anyone with some level of understanding with FPGAs who wants to increase the knowledge and experience of the tool chain and processes for development.
Design Engineer - Space Systems
The course covers a good selection of subjects on FPGA for newcomers to the industry. As well as explaining the basics of how FPGAs work and their purpose, it also gives an idea of the more advanced techniques that can be used in their development. Even people with some experience could get some ideas from here.
Head of Digital Systems - Communications
The ability to design and work with effectively with FPGA based circuit cards is critical for FPGA engineers. This course is aimed at giving attendees the ability to get to grips with key design decisions, standards, considerations, and trade-offs to enable the development of FPGA based solutions along with how to approach the testing and verification
£1,200 per attendee
5 day course
Due to the length and depth of the course the delivery is split over a number of sessions and not delivered in a continuous block.
Online dates for 2025:
April 7th - 11th
July 14th - 18th
October 3th - 17th
Electronics for FPGA Development
Architectures, Requirements, Verification, ICD
System Level Concepts which are used to develop and guide the hardware process
Clocking and Pin Planning
Getting it right saves us a lot of pain later on
FPGA Estimation
-
How to estimate the logic resources required
-
How to estimate the Power required for input into the power budget
Digital Signals
-
• Standards
- Unbalanced
- Balanced
- Common-mode & differential voltages
- Matched
- Unmatched
- Drive level
- Slew rate
- Loading
• Banking
• SSO limits
• Slew rate / Schmitt-trigger
• Switch bounce
• IO Banking Rules
Memories
-
How to design in DDR3 / 4 Memories – Early verification
-
Power and Termination Schemes
-
Routing Rules and Importance of PI/SI
-
Configuration memories and non-volatile memories
-
SRAM Memories in place of DDR 3 / 4
Working with ADC and DAC
-
ADC / DAC selection
-
ADC / DAC parameters e.g. SFDR, SNR ENoB
-
ADC/DAC test Strategies
EMC / Signal integrity
-
What is EMC and what are we trying to do
-
What is signal integrity and how do we address it
-
What is power integrity and how do we address it
-
Minimizing interference both with the external world and FPGA
-
Reflections and avoiding them
ESD
-
What is it and why should we worry about it
-
Protection devices - choose carefully to avoid limiting performance
Power Supplies
-
Selecting the most appropriate power supplies
-
SMBus
-
Accuracy
-
Noise
-
Sequencing
Design Analysis
-
The importance of Design Analysis in the flow
-
How to conduct Part Stress Analysis
-
How to conduct FMECA
NOTES
-
This course does not teach techniques for the design of the FPGA functionality
-
All attendees will receive a copy of the book A Hands on Guide to Designing Embedded Systems (Artech House 2021)
Online dates for 2025:
April 7th - 11th
July 14th - 18th
October 3th - 17th
Architectures, Requirements, Verification, ICD
System Level Concepts which are used to develop and guide the hardware process
Clocking and Pin Planning
Getting it right saves us a lot of pain later on
FPGA Estimation
-
How to estimate the logic resources required
-
How to estimate the Power required for input into the power budget
Digital Signals
-
Standards
- Unbalanced
- Balanced
- Common-mode & differential voltages
- Matched
- Unmatched
- Drive level
- Slew rate
- Loading -
Banking
-
SSO limits
-
Slew rate / Schmitt-trigger
-
Switch bounce
-
IO Banking Rules
Memories
-
How to design in DDR3 / 4 Memories – Early verification
-
Power and Termination Schemes
-
Routing Rules and Importance of PI/SI
-
Configuration memories and non-volatile memories
-
SRAM Memories in place of DDR 3 / 4
Working with ADC and DAC
-
ADC / DAC selection
-
ADC / DAC parameters e.g. SFDR, SNR ENoB
-
ADC/DAC test Strategies
EMC / Signal integrity
-
What is EMC and what are we trying to do
-
What is signal integrity and how do we address it
-
What is power integrity and how do we address it
-
Minimizing interference both with the external world and
FPGA -
Reflections and avoiding them
ESD
-
What is it and why should we worry about it
-
Protection devices - choose carefully to avoid limiting
performance
Power Supplies
-
Selecting the most appropriate power supplies
-
SMBus
-
Accuracy
-
Noise
-
Sequencing
Design Analysis
-
The importance of Design Analysis in the flow
-
How to conduct Part Stress Analysis
-
How to conduct FMECA
About your instructor
Barry Cook is a world recognised expert in electronic systems design, particularly - but not only - for the Space Industry. His skills range from analogue electronics, through digital, FPGA and software. Notable designs are to be found in the existing RASAT and Flying-Laptop satellites - and forthcoming PLATO and ERSA missions.
He also has 18-years experience as a Lecturer / Senior Lecturer in Computer Science and Information Systems Engineering at London, Surrey and Keele Universities.
Barry has a Degree in Computer Science and Electronic Physics, a PhD for research in Image Processing, is a Chartered Engineer and Chartered IT Professional, Member of the IEEE and BCS, and is a Fellow of the British Interplanetary Society. His publication list includes 70+ papers in journals and international conferences, 6 books, and 19 granted patents for 4 basic inventions,