MicroZed Chronicles: Creating Image Processing with Simulink

One of the things I have been meaning to write about for a while now is an update to the Alinx Versal AI Edge 2302 VD100 development board project, which displayed a test pattern on an attached LCD display.

The update to the project was to include an Alinx camera and create an image processing pipeline which enables live video to be captured by the camera and displayed on the LCD. Having the output pipeline already established, this is a relatively simple update to the design.

To be able to capture the video, we first need to implement the following IP cores:

To be able to capture the video, we first need to implement the following IP cores:

• MIPI CSI-2 RX Subsystem – Configured for four lanes, 10 bits of RAW data, outputting four pixels per clock

• Sensor Demosaic – Configured for four pixels per clock and 10 bits of RAW data

• Video DMA (VDMA) – Connected to read and write frames from the DDRMC over the NoC

• CIPS I2C via EMIO – Enabled to allow camera configuration

• 
  

Once these are instantiated and connected, we have an image processing pipeline which can pass video through from the camera to the LCD. Of course, we also need software to configure the camera over I2C, configure the processing cores, and control the Video DMA. The completed design can be seen below and has been shared on my GitHub

When running the application, the output image is displayed on the screen; however, it is obvious that it requires gamma and white balance correction.

What I really wanted to do, however, was create a simple image processing algorithm which could be dropped into the design. For this, I selected a Sobel edge detection filter implemented using MathWorks Simulink HDL Coder.

To get started, I created a new subsystem in Simulink which would be converted into an HDL IP block for Vivado.

The Sobel algorithm operates on a grayscale input, so the first step is to convert the RGB colour space into grayscale. The module is designed to use AXI4-Stream video data in and out. This means a 24-bit pixel on the tData line (combining RGB pixels, each 8 bits) along with the control signals (tUser, tLast).

Once the image has been converted to grayscale, we are able to use the Sobel block to indicate when an edge is detected. To create the output pixel value, I use the output of the Sobel edge detection to drive a switch which outputs either 0 or 255.

This approach enables us to simulate the design by feeding in a video and demonstrating the algorithm. To do this, we can use the From Multimedia File block, followed by a Frame to Pixels conversion block. This converts the video frame into two outputs: one containing the pixel data and another containing the control signals, including timing information.

On the output side, to view the processed image, we need to perform the reverse operation using the Pixels to Frame block. We can then use a video viewer to see the processed video.

However, a small conversion is required: the Frame to Pixels output is in a uint8[1x3] format, which is a 1-by-3 row vector of uint8. To map this to an AXI4-Stream interface, we require a single uint32 input.

To achieve this, I created a small MATLAB script which converts the 1x3 uint8 array into a uint32. While a 24-bit type would be ideal, this is not supported by MATLAB. The first element of the block intended for HDL generation performs the reverse operation, splitting the uint32 back into a uint8[1x3] array.

Using this approach, we can configure the interfaces to use AXI4-Stream for video.

Running the simulation shows the output video correctly detecting edges.

With that complete, we are able to generate the HDL IP core using HDL Coder. As we are targeting an AMD Vivado IP core, this provides everything required to drop the block directly into the Vivado design.

The IP core is then added to the Vivado design. As it processes a single pixel per clock, I inserted it into the output pipeline downstream of the VDMA.

The block does not require many resources: approximately 5 DSPs, 1,606 flip-flops, and 941 LUTs. In this design, it is clocked at 200 MHz, which presents no issues for timing closure.

Running the updated design, with the Vitis embedded software modified to configure the edge detection IP block, shows the output image with edges clearly detected. This is updated and displayed at a 60 Hz frame rate.

I have shared the design on GitHub, and the Sobel filtering block should work for most resolutions, as it is software configurable.

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