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NEW RELEASE:
AI Training

Master the complete AI pipeline, from core theory to hardware deployment. Led by an embedded AI expert, in this course you will learn to build, train, and evaluate your own models on resource-constrained devices for real-world application.

£2,000 per attendee
5 day course

Due to the length and depth of the course the delivery is split over a number of sessions and not delivered in a continuous block.

Online dates for 2025:
October 20th - 24th

Course components

Module 1: Machine Learning Basics

  • Supervised, unsupervised, reinforcement learning

  • Regression and classification

  • Loss functions, overfitting, regularization

  • Model evaluation (cross-validation, metrics)

Module 2: Core Algorithms

  • Decision Trees

  • k-Nearest Neighbors

  • Naive Bayes

  • Support Vector Machines

  • k-Means clustering

Module 3: Neural Networks & Deep Learning

  • Perceptron and multi-layer networks

  • Activation functions

  • Backpropagation

  • Intro to CNNs, RNNs

Module 4: Building & Using Pretrained Models

  • Model construction with TensorFlow (Sequential API for CNNs)

  • Building a simple CNN for image classification

  • Loading and using a pretrained model (e.g. ResNet50 or MobileNet)

  • Modifying the output layer for a custom dataset

  • Training both models on the same dataset

  • Comparing performance: accuracy, loss, and training time

Module 5: Deployment & Hardware Evaluation

  • Exporting TensorFlow models (SavedModel, TFLite)

  • Deploying models on Raspberry Pi (setup, dependencies, accelerators)

  • Running inference with a pretrained ResNet and a custom CNN

  • Measuring latency, memory usage, and power consumption

  • Comparing performance: pretrained vs. user-built model on edge hardware

Online dates for 2025:

October 20th - 24th

FPGA Requirements and processes flow

  • What is engineering governance

  • Review Processes / Check Lists / Gate Reviews

  • Example Review Stages e.g. SRR / PDR, CDR, etc

  • Standards we might work with

  • Do254 / iec61508 / iso26262

  • Safety integrity Level

  • Failure Space

  • System engineering V Model

  • Challenges of environments – Temperature, Vibration, Radiation, EMC

Systems Engineering

  • What makes a clear requirement

  • Levels of Requirement

  • Cross Referencing

  • Engineering Budgets

  • Verification Strategies

Architecting the FPGA – how to approach the architecture of the device

Key elements of FPGA Architecture

  • IO planning

  • Clocking

Architectures and considerations

  • Global, Regional, Source Synchronous Clocks

  • IP Blocks, Reuse, standardisation

  • Interconnect technology AXI, APB, Wishbone

  • External interfaces I2C, SPI, UART

  • Bridging external to internal interfaces and technology

  • Complex memories e.g DDR3, DDR4

  • How to define architectures & registers - Using SysML

  • Clock Domain Planning and safe CDC analysis

  • Documenting the architecture

  • IO – Standards, Drives, Pulls

  • Clocks

  • Memory Map

Documentation for modules required 
to be developed

  • IO

  • Clocking

  • Registers

  • Error conditions and failure cases

Verification strategies

  • Planning for verification

  • Verification Documentation

  • Commonly used frameworks

  • UVM

  • UVVM / OSVM

  • Cocotb

  • Corner cases and boundary conditions

  • Constrained random

  • Code Coverage

  • Self-Checking Test Benches

  • Independence in verification

Constraints

  • What is the purpose of constraints – Physical and timing

  • Where do we use constraints

  • Synthesis – Control Optimisation etc

  • Placement – Control physical placement and location

  • Advanced e.g. Partial Reconfiguration / Isolation Flow

FPGA initial design skills

  • How to design FPGA using VHDL

  • Leverage Packages / Libraries / procedures and functions

  • FSM Styles – Single Process, Safe State Machines,

  • Counters – Coding for performance, safety

  • Pipelining,

  • Working with BRAM and DSP

FPGA advanced skills

  • Clock domain crossing,

  • Coding for security / reliability 

  • FSM

  • SECDED on Memories,

  • Isolation flow, TMR,

  • FPGA Mathematics

  • IO structures – I/OSERDES, DDR etc

IP Usage

  • When and where is it appropriate to IP

  • How to integrate IP in your design to enable portability

Softcore processors

  • Creation of MicroBlaze solution in FPGA

  • Debugging MicroBlaze

  • Integrating with IP

  • Real Time, Interrupt Driven Processing

  • Boot and Configuration Options

System on Chip Design

  • Creation of Zynq / MPSoC based systems

  • Basic intro to SoC system creation

  • FPGA /SW integrations and communication

  • Embedded Linux

  • Debugging – Cross Probing

Timing Analysis

  • What is STA

  • How to find failing paths

  • Correction of issues

  • Routing vs Logic

  • How to analyse IO timing

Debugging on Hardware

  • Considerations for board bring up

  • Debug methodology and how to debug a design

  • Use of ILA

GET IN TOUCH TO BOOK OR DISCUSS

Online dates for 2025:

April 7th - 11th

July 14th - 18th 

October 3th - 17th

About your instructor

Dr James Murphy

Dr James Murphy is an expert in embedded systems and AI for space and edge computing applications. With deep experience across both industry and academia, he specialises in deploying machine learning solutions in resource-constrained environments.

James holds a PhD in Computer Science from the University College Dublin, where his research focused on AI based on-board anomaly detection for spacecraft. He has also held multiple visiting researcher positions at the European Space Agency (ESA), contributing to advanced autonomy and AI initiatives across several ESA centres.

​

Currently, James is the AI Engineering Lead at Réaltra Space Systems Engineering and has led the development of critical flight and ground software for European launch vehicles, including the first full HD live-stream camera system used on Ariane 5 during the launch of the James Webb Space Telescope. His technical expertise spans embedded C, Python, and deep learning frameworks such as TensorFlow and PyTorch, with real-world deployment on ARM Cortex, Jetson, and Raspberry Pi platforms.

What attendees have said 

The FPGA training course I did online was very well presented by Adam Taylor and followed a logical progression that was easy to understand. Adam was more than willing to answer questions. The exercises were at a good level, and also followed a logical process.

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I learned a lot during the course and would recommend the course to anyone with some level of understanding with FPGAs who wants to increase the knowledge and experience of the tool chain and processes for development.

Design Engineer - Space Systems

I wasn't sure if the class was for me before starting it. Coming from the verification background, I needed some experience dealing with vivado and learning design principles of FPGAs. The class was amazing, it met all of my expectations. The course teacher, Adam Taylor was very patient and knowledgeable. He is willing to answer any questions regarding FPGAs. The best part about the course is all the labs and lectures are available to you forever and Adam mentioned that you can still reach out to him for questions. There are also more labs available on https://www.hackster.io/adam-taylor that you can follow and do for more learning. I enjoyed the class very much. 10/10.

IC Design Engineer - Semiconductors

The course teacher, Adam Taylor, has extensive experience from the most advanced projects in the world. There is hardly anyone else available to learn from to such an extent, since his expertise is unique and rounded. He is actively working on most complex projects, bringing you to the forefront of todays FPGA design methods and practical engineering skills and tips.

Electronics Engineer - Defence

The course covers a good selection of subjects on FPGA for newcomers to the industry. As well as explaining the basics of how FPGAs work and their purpose, it also gives an idea of the more advanced techniques that can be used in their development. Even people with some experience could get some ideas from here.

Head of Digital Systems - Communications

Adam delivers the content with just the right pacing to cover the most important aspects of working with FPGAs. The course forms a very solid basis for then exploring the topic even deeper at your own pace using the hand-out materials and lab-exercises provided during the course.  The highest value for us was being able to discuss with Adam, who is generously sharing his experience about the best tools and strategic approaches to tackle the development of complex and often safety critical FPGA based systems. 

Embedded Systems Engineer - Healthcare

I thoroughly enjoyed the course. It was at the right pace, and an ideal introduction to FPGA technology

Electronics Engineer - Industrial

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