Adam Taylor

FPGA Conference - FPGA Horizons US East - April 29th, 30th 2026 - THE FPGA Conference, find out more and get Tickets here . Recently, we have looked at how we can use AI in our RTL development and in our software development within Vitis . AMD is also going to be running a very interesting tutorial on upcoming AI features within FPGA at FPGA Horizons US . This got me thinking that I should write a little more about how I am using it and the flow I am using in my developments. The first...

One of the recurring themes across many of my blogs and projects is the development of image processing solutions. Typically, these solutions are output to a display—most often HDMI, and occasionally DisplayPort. DisplayPort is particularly useful for MPSoC-based image processing applications because it is integrated within the Processing System (PS) of the device and outputs via the PS GTR transceivers. Using the PS DisplayPort, we can generate graphics from DDR memory, output live video...

Over the last few weeks and months I have found myself working on several Versal designs. One of the most important aspects of working with Versal devices is having a verification strategy. Versal devices are impressive with the combination of the CIPS, AIE and PL, to get the best from the device our solution often uses a combination of these diverse processing elements. While working on these projects I have also been exploring the verification capabilities available within Vitis and Vivado....