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MicroZed Chronicles: ePaper Testing and Integration

In our last blog we discussed an E Ink / ePaper driver that I had designed. Today we are going to discuss how to integrate it with a Zynq Z7 on an Arty Z7-20 and test that we can drive the display correctly.

 

The basic idea is that the IP core reads the display settings from a BRAM located externally to the IP core. This means we can configure the BRAM as a ROM using a COE file if the display is not to be updated in run time or reconfigured by changing the BRAM contents during run time.

 

To get started, I am going to create a block diagram which contains a Zynq-7000 processing system. We are going to connect the following from the Zynq PS Master AXI Interconnect:

  1. AXI GPIO – This will provide the reset pulse to the ePaper.

  2. AXI GPIO – This will provide the run signal to the ePaper IP.

  3. AXI BRAM Controller – This will control the BRAM used to set the output display.

 

The sizing and interfacing with the BRAM is interesting. The display we are using has 200 by 200 pixels and each pixel can be either 1 or 0 setting to white (1) or black (0). This means we need 40,000 bits or 5000 bytes to output on the image. This will easily fit within BRAM since we are able to write to the BRAM and update patterns using the AXI BRAM controller. This means we can test patterns on the display to demonstrate if the IP block is working correctly.

 

Organization of the BRAM is different to a standard configuration when used with a BRAM controller. We want to be able to write in 32 bits to port A from the processor but the IP needs only 8 bits at a time. This means we need to configure the ports as asymmetrical, 32-bit write and 8-bit read dual port.

 

We therefore need a 8K byte address space from the processor, however the address increment is 0x4 since we are writing 32-bit words. This addressing is passed through the AXI BRAM controller. As a result, this would lead to addresses in the RAM being unused which would lead to corruption in the E Ink display.


To address this issue and ensure interoperability with the BRAM controller, I use a slice to remove the least significant two address elements. I am mentioning this in detail because I have seen a few questions related to the AXI BRAM and BRAM addressing when using BRAM configured as standalone.

 

The final design for testing is as follows.

With this design and simple C code below created in Vitis, we are able to test the E Ink IP. The tests I used were pretty straightforward. Simply set the entire display to black, clear the display and draw some lines on the display.

#include <stdio.h>
#include <xil_io.h>
#include "platform.h"
#include "xil_printf.h"
#include "xparameters.h"
#include "xgpio.h"

XGpio reset;
XGpio run;

#define bram_base   0x40000000
#define bram_max    2048
#define offset      0x4

int main()
{
    init_platform();
    XGpio_Initialize(&reset, XPAR_XGPIO_0_BASEADDR);
    XGpio_Initialize(&run, XPAR_XGPIO_1_BASEADDR);

    u32 addr = bram_base;

    for( int i = 0; i < bram_max; i++){

        //if (i >500 & i < 520){
        //    Xil_Out32(addr, 0x00000000);
        //}
        //else
            Xil_Out32(addr, 0x00000000);
        addr = addr + offset;
        usleep(100);
    }

    XGpio_SetDataDirection(&run,    1, 0x0 );
    XGpio_SetDataDirection(&reset,  1, 0x0 ); 
    XGpio_DiscreteWrite(&run,   1, 0x00);
    XGpio_DiscreteWrite(&reset, 1, 0x01); 
    usleep(1000000);
    
    XGpio_DiscreteWrite(&reset, 1, 0x00); 
    usleep(10000);
    XGpio_DiscreteWrite(&reset, 1, 0x01); 
    
    usleep(1000000);    
    XGpio_DiscreteWrite(&run, 1, 0x01); 
    usleep(1);
    XGpio_DiscreteWrite(&run, 1, 0x00); 

    while(1){

    } 

    cleanup_platform();
    return 0;
}

This shows that the basics of the E Ink IP block are working as expected.





Now I can start to think about how I will create a little application which allows C Header or COE files to be generated based on what we’d like displaying on the screen.


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