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MicroZed Chronicles: Vivado Simulator Code and Functional Coverage

While writing the HDL is often the easy element of FPGA development, the most challenging and time-consuming element can be verification. Depending upon the end application, the verification could be as easy as running a simple check of most functionality or performing a full independently developed test bench demonstrate both functional and code coverage.

Functional and code coverage are important in verification because they both provide information on different aspects of the design and its verification. Ideally, we want both to achieve 100% of both. Achieving 100% of only one or the other separately indicates that we have further verification work to do.

If you are unfamiliar with code and functional coverage, here are the common definitions.

  • Code coverage – Provides information on how well the test bench exercises the unit under test. For example, it can indicate if all branches and statements get traversed if are all flip flops are toggled. etc.

  • Functional coverage – Provides information on how well the test bench covers the functional behavior of the unit under test. To achieve this, the developer / verification engineer must define the cover groups and coverage points.

The difference between code and functional coverage is that functional coverage requires the use of the requirements.

Of course, both code and functional coverage require effort and planning. Code coverage can have some limitations because it does not identify missing functionality and cannot identify if all possible boundary / corner case values have been addressed. Code coverage also does not care about the sequence of events which might mean they don’t occur in the correct sequence. This is where functional coverage comes into play as it enables declaration of functionality to be tested.

Typically, code and functional coverage needs an expensive simulation tool, however, both are possible with the Vivado simulator from Vivado 2021.1. When working with Vivado, this gives developers significant capabilities to verify their design and ensure the RTL functions as required.

For code coverage, one of the first things we need to do in the project settings, under the simulation tab and elaboration setting is to set the coverage type. In the Vivado simulator we can set the following options:

  • Line / Statement (s)

  • Branch (b)

  • Condition (c)

  • Toggle (t)

We can also define the coverage report name and the location of the coverage directory.

Running the simulation will then generate the coverage information at the end of the simulation run. You will be able to see the codeCov directory at the location specified in the elaboration settings because I left this under the default simulation directory.

To create functional coverage, we will need to create coverage groups within the RTL.

This is the data base to get the report. We need to do a little more processing in Vivado to covert the data base to a report.

If you want to take a look at the capabilities of the Vivado simulator with functional and code coverage, the best starting point is UG937 Vivado Design Suite Tutorial: Logic Simulation. This provides several design examples which can be used to test out the different aspects of the Vivado simulator’s capabilities which include code / functional coverage and also UVM support.

The functional and code coverage example is based around the AXI VIP reference design. Following through the tutorial and adding in the cover group will provide functional and code coverage.

Once the simulation is complete, we need to run xcrg command to create the HTML report.

The resultant HTML report can be opened in any browser

Clicking on the groups button will open detailed information on the coverage groups which is pretty simple in this example.

Running the code coverage conversion the resultant code coverage report can be seen.

Clicking on the files will show the results per file.

All told, I’m impressed with the capabilities of the Vivado simulator. Using these features will help developers create the best quality design and hopefully result in less time spent debugging hardware.

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