MicroZed Chronicles: Vivado Simulator Code and Functional Coverage
While writing the HDL is often the easy element of FPGA development, the most challenging and time-consuming element can be verification....
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Adam Taylor
- Jan 11
- 8 min
MicroZed Chronicles: From UART to AXI Lite Debug Access
Last week we examined how we could create a UART with AXI Stream interfaces to enable access to AXI buses in device for debugging. In...
Adam Taylor
- Dec 30, 2022
- 3 min
Using RPI Pico for System & FPGA Integration
Several times in recent blogs and posts on LinkedIn and Twitter I have mentioned that at Adiuvo we use a lot of RPI Pico’s for hardware...
Adam Taylor
- Sep 6, 2022
- 5 min
MicroZed Chronicles: Getting Started with Cocotb
Verification of both the modules and top-level testing is often more complex and time consuming than creating the HDL. Previously, we’ve...
adam@adiuvoengineering.com
- Mar 26, 2021
- 1 min
Electronic Engineering Guide - A 57 Page Guide
A simple engineering guide which covers Electronic Design Flow Capacitor and Resistor Selection Grounding Power Distribution Thermal...
Adam Taylor
- Jan 14, 2021
- 3 min
MicroZed Chronicles: GHDL and UVVM Framework
In this post, we will expand the use of GHDL with an open-source verification framework for VHDL called UVVM.
Adam Taylor
- Jan 7, 2021
- 3 min
MicroZed Chronicles: Installing and Working with GHDL for Verification
In this blog let's look at how to install GHDL and use it to simulate our VHDL designs.
Adam Taylor
- Nov 4, 2020
- 3 min
MicroZed Chronicles: AXI Stream Verification IP
The AXI Stream VIP is extremely useful when we want to generate signal and image processing IP that use AXI Stream for interfacing.
Adam Taylor
- Oct 28, 2020
- 4 min
MicroZed Chronicles: Verifying AXI Peripherals
The designs we implement in Vivado often use AXI interfaces. These might be AXI Lite for configuration and control, AXI Memory Mapped
adam@adiuvoengineering.com
- Sep 23, 2020
- 4 min
MicroZed Chronicles: Introduction to RTL Simulation and XSIM
No matter how captured (RTL, HLS, Model Driven), all programmable logic designs should start with agreed requirements that define the...
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