When developing FPGAs there is a critical triad which needs to be achieved for the successful delivery of a project. First we need to...

One of the things I enjoy is when people reach out with suggestions for blogs and projects that would help them. A recent suggestion was...

While writing the HDL is often the easy element of FPGA development, the most challenging and time-consuming element can be verification....

Last week we examined how we could create a UART with AXI Stream interfaces to enable access to AXI buses in device for debugging. In...

Several times in recent blogs and posts on LinkedIn and Twitter I have mentioned that at Adiuvo we use a lot of RPI Pico’s for hardware...

Verification of both the modules and top-level testing is often more complex and time consuming than creating the HDL. Previously, we’ve...

In this post, we will expand the use of GHDL with an open-source verification framework for VHDL called UVVM.

In this blog let's look at how to install GHDL and use it to simulate our VHDL designs.

The AXI Stream VIP is extremely useful when we want to generate signal and image processing IP that use AXI Stream for interfacing.

The designs we implement in Vivado often use AXI interfaces. These might be AXI Lite for configuration and control, AXI Memory Mapped

No matter how captured (RTL, HLS, Model Driven), all programmable logic designs should start with agreed requirements that define the...