top of page
Adiuvo Engineering & Training logo
MicroZed Chronicles icon

MicroZed Chronicles: Scripting

When it comes to professional FPGA development, our designs need to be stored in source control to ensure repeatability. We have looked previously at how we can do this using Git and Vivado however, that is just one element of it.

 

For example we may generate embedded software for the Zynq, Zynq MPSoC, or Versal hard processor cores. This may be ether bare metal, RTOS or embedded Linux solution as such being able to build the deployable image easily and repeatability is critical.

 

We also may need to deliver to the client a package which easily allows them to rebuild the complete system. To do this well we should be able to provide a simple document which defines the environment and tools required to be installed and then provide a script which recreates the entire design.

 

When we are working with Vivado, Vitis and PetaLinux we are able to create scripts which will once run will create projects, add source files and of course build and create deployable images.

 

To create a script that generates the deployable image we can use make, this is the simplest way and allows us to define one or several commands to build either the complete deployable image or sections of it.

 

Over this blog and the next we are going to look at how we can do this with a simple MicroBlaze Risc V design in a Arty S7-50.

 

In this blog we are going to look at how we can create the hardware element of the design and generate the XSA such that in our next blog we can examine the software scripting and deployable image creation.

 

The first thing we need to do is build a MicroBlaze Risc-V design as below.


ree

Before creating the scripts it is a good idea to ensure the project does build, to prevent chasing simple issues later on.

 

Once the project has built the next step is to export the block design as a TCL script.


ree

Once we have this script we are in a position that we can create the remaining TCL and make scripts. I have purposely kept the scripts as simple as could possibly be to show the flow, you might want to add more features into your actual deployment.

 

I am going to have a tiered make file approach there will be one overall make file and separate ones for the HW and SW builds.

 

As we are focusing on the HW build for this project the main make file looks as below, this defines file locations and it also calls the lower level HW make file

 

.PHONY: build_hw
build_hw:
	$(MAKE) -C hw

 

The HW make file looks as below

 

.PHONY: build_design
build_design:
	@echo "Building hw design"
	vivado -mode batch -source scripts/build_all.tcl

We also need to create a couple of additional TCL scripts along side the one which was automatically created.

 

Build_all.tcl  - This script is the overall script which controls the series of events and is called directly by the hw make file. Remember if you are using a board which has been downloaded you will need to set the board repo path before creating the project.

 

source ./scripts/build_proj.tcl
source ./scripts/run_impl.tcl

 

Build_proj.tcl – This is the script that creates the project and calls the TCL script exported from Vivado previously.



set_param board.repoPaths {<board repo path>}

create_project -force vivado/system . -part xc7s50csga324-1
set_property BOARD_PART digilentinc.com:arty-s7-50:part0:1.1 [current_project]
update_ip_catalog

source scripts/pl_design.tcl

set bdwrapper [make_wrapper -files [get_files system.bd] -top]
add_files -norecurse $bdwrapper
update_compile_order -fileset sources_1

add_files -fileset constrs_1 -norecurse xdc/io.xdc

validate_bd_design
save_bd_design

This file, builds the IP integrator design and then creates the HDL wrapper and adds in the constraints to the project before validating and saving the design.

launch_runs impl_1 -to_step write_bitstream -jobs 8

wait_on_run impl_1

open_run impl_1
write_hw_platform -fixed -force -file system.xsa

This starts the implementation and exports the XSA.


ree

By the completion of the run implementation script we are ready to be able to create the software application and deployable image in the next blog.



UK FPGA Conference


FPGA Horizons - October 7th 2025 - THE FPGA Conference, find out more here.



Workshops and Webinars:


If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include:




Boards


Get an Adiuvo development board:


  • Adiuvo Embedded System Development board - Embedded System Development Board

  • Adiuvo Embedded System Tile - Low Risk way to add a FPGA to your design.



Embedded System Book   


Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here   Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.


Sponsored by AMD 

bottom of page