Normally, we clock the logic within our FPGA design using clocks either provided externally or generated internally using MMCMs, PLLs, or...

Every digital / FPGA designer should be aware of clock domain crossing between asynchronous clock domains. As our devices get more and...

We all know that if we want to get the best performance, we should place input clocks to our FPGAs on clock capable or dedicated clock...

Over the last few weeks, we have looked at some interesting aspects of the 7 series and UltraScale / UltraScale+ clocking buffers. To...

Last week we looked at how we could use 7 series clocking resources to provide integer clock division without using MMCM. In this week’s...

Many of our FPGA designs are multi-clock, meaning several clocks within the design, which can introduce clock domain crossing challenges....

Clocking is at the heart of every FPGA design.. We can spend a lot less time battling the tools if we get the clock architecture right,...

When I started my design career twenty plus years ago, one of the very simple rules we had for significantly smaller and less flexible...