MicroZed Chronicles : What do I actually do?

I am a regular contributor to many FPGA channels. A few days ago, someone posted a question about what FPGA consultants actually do. The answer, of course for anyone who has run their own business is pretty much anything that keeps the lights on and pays the bills.

Turnkey delivery (fixed-price).

Generally, however, it can be split into two elements. The first element is performing design services for example, designing an IP block or a complete FPGA design. Typically, for Adiuvo, I do these as fixed-price developments: we agree the requirements, milestones, and delivery, and away we go to deliver the FPGA. This approach means I control when we work, where we work, and the development flow we use. This means we can develop using our system and flow, which is familiar and often better than the client has available. Occasionally we will be asked to use a customer’s IT, but typically that impacts cost and timescales. We take this approach not only for FPGA but also for boards and embedded software.

Get-it-over-the-line (time & materials).

The second type of engagement is where someone else, either internally or externally, has already developed the FPGA, and help is needed to get it over the final hurdle. This could be addressing functional or timing bugs. Engagements for me in this case tend to be when another engineer has developed the FPGA and made a complete mess of it. Typically, we engage on these projects at an hourly rate as the design is investigated and corrected.

To give a little more context, let’s take a look at what I actually did over the last week (11th–15th August). This week was busy but very productive.

Monday – Reference designs & AXI/ SmartConnect sleuthing

I spent Monday in the office from about 9 am to 10 pm. I am working on three reference designs for the SCU35 board. I spent most of the day putting the finishing touches to one of the designs and ensuring it worked on the SCU35, having been prototyped on the ZU Board. While doing this, I encountered an issue when updating the AXI Interconnect to SmartConnect, which changed the AXI transaction delay and consequently corrupted the output SPI word. A few simulations, however, ensured the issue was identified and corrected. Monday evening was spent on calls with clients in the US; I had four separate calls, all lasting about an hour, looking at projects we are working on.

FPGA – Spartan UltraScale Plus

Tuesday - On-site debug in Wales

One of our debugging contracts is for a client in Wales, about a four-hour drive away. We have been helping them correct a military vision FPGA system. They had an issue with the legacy code not driving one of the critical actuators correctly, so the only thing for it was to jump in the car and go and look at the real-world system and how it interacts with the FPGA via a complex chain of motor-control electronics. An early start and lots of driving; however, once I arrived, the issue was pretty straightforward, and we were able to identify the issue with the legacy code, correct the design, and leave it functioning as desired.

FPGA – Artix 7

Wednesday - Scoping a high-voltage power project

This started with a business development meeting. I went to visit a potential (hopefully soon-to-be) client; I had quoted on an FPGA project related to a high-voltage power system. Both sides thought it would be a good idea to get together and talk through the requirements and approach. I am glad we did this, as it resulted in the system becoming a little easier than we initially thought. The downside was that, on the drive back, I got stuck for three hours on the M25 behind a lorry fire. Wednesday evening, I spent back in the office working on the reference designs again.

FPGA – Still TBC, but likely to be an Artix-7 FPGA with a transceiver.

Thursday – Image sensor bring-up & delivery

Another and what I thought was my final trip out of the office this week. We have been developing an upgrade to an image-processing solution for a client. We needed to test the FPGA design with the actual image sensor. After a few minor tweaks to how the IODELAY2 block was being driven by the software, the application was working as expected and the project was delivered.

FPGA – Spartan 6.

Friday – SBC platform integration

An unexpected day out of the office. We have been helping a large single-board computer developer create the FPGA for their latest offering. The initial drop was delivered, but, as always with these things, items that were not in the spec come up and need to be integrated and tested. This is one of the most complex PCB designs I have seen; the engineering is phenomenal, and the FPGA plays a crucial part in the management of the board.

FPGA – Artix 7

Saturday and Sunday – Content & R&D

I spent the weekend in the office working on many of the other projects I am currently working on. These include a Hackster project on functional simulation in Vitis, this week’s blog, an article for a distributor, and, of course, experimenting and investigating new boards and projects.

In total, I worked with six different FPGA projects this week and drove over 1,000 miles (not much for the US, but a lot for the UK). I also had to keep in touch with staff and contractors working for me in Ireland, the US, and the UK; keep my accountant happy by explaining what I actually spent the money we make on development boards and test equipment; plan for the week ahead; and, of course, organise the UK FPGA Horizons conference. We finally signed for the US event, also to be held in Massachusetts in 2026.

A bit of a busy week, but nothing too bad; at least the travel was local, and for most things we got closure and delivery, which is also good. The pipeline looks very healthy.

Next Steps

This exercise has “pipeline-cleaned” the workflow from network definition in MATLAB to deployment and testing on hardware. With the process established, I can now explore transfer learning for more complex machine learning applications, applying the same methodology.

UK FPGA Conference

FPGA Horizons - October 7th 2025 - THE FPGA Conference, find out more here.

Workshops and Webinars:

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include:

• Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal

• Professional PYNQ Learn how to use PYNQ in your developments

• Introduction to Vivado learn how to use AMD Vivado

• Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux

• Arty Z7-20 Class looking at HW, SW and PetaLinux

• Mastering MicroBlaze  learn how to create MicroBlaze solutions

• HLS Hero Workshop  learn how to create High Level Synthesis based solutions

• Perfecting Petalinux  learn how to create and work with PetaLinux OS

Boards

Get an Adiuvo development board:

• Adiuvo Embedded System Development board - Embedded System Development Board

• Adiuvo Embedded System Tile - Low Risk way to add a FPGA to your design.

• SpaceWire CODEC - SpaceWire CODEC, digital download, AXIS Interfaces

• SpaceWire RMAP Initiator - SpaceWire RMAP Initiator,  digital download, AXIS & AXI4 Interfaces

• SpaceWire RMAP Target - SpaceWire Target, digital download, AXI4 and AXIS Interfaces

• Other Adiuvo Boards & Projects.

Embedded System Book   

Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here.  Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.

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