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MicroZed Chronicles: Spartan UltraScale+ and the SCU35 Board

The Spartan UltraScale+ family is designed to provide developers at the edge with a wide range of interfacing solutions, coupled with high performance and low power. As always, as engineers we are challenged to increase performance with tighter power and thermal constraints. Edge deployment also means the systems are easily accessible to unauthorised third parties. Spartan UltraScale+ devices provide developers with solutions intended for the post-quantum age.

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Architectural Details


That is the high-level overview of the device. Where it gets very interesting is looking at the detailed architecture. The device is fabricated on the 16 nm node, in line with the other UltraScale+ range. There are some significant differences which make it a very interesting family. We will see the return of transceivers to Spartan devices, with up to 8 transceivers supported at line rates of 16.375 or 12.5 Gb/s. We also see High Definition I/O (HDIO) and High Performance I/O (HPIO), but we also see the inclusion of the XP5IO.

Within the programmable logic, we also benefit from the UltraScale architecture. When it comes to DSP, designers are provided with DSP48E2, which offers wider multiplier and pre-adder inputs. Along with BRAM resources, larger devices within the range also benefit from larger UltraRAM blocks, which can provide better storage of larger data elements.


Integrated Hard IP for High Performance


Crucially for high performance, and to ensure the logic can be leveraged for the application in hand, there is an integrated memory controller, hard in the silicon, which supports LPDDR4/5. In a similar manner, there is also a hard PCIe controller. These integrated memory and PCIe controllers ensure reduced overall power dissipation, as implementations are not being done in a soft manner within the programmable logic. As I mentioned before, this also means our programmable logic resources go further, as they are not being used for infrastructure-type activities.


Introducing the SU35P and the SCU35 Development Board


One of the first devices which will populate a development board is the SU35P, which offers:

  • 36K logic cells

  • 48 DSPs

  • 48 BRAM

  • Up to 304 I/O

This device will be populated on the SCU35, which provides developers with a range of interfaces, including:

  • Four Pmod interfaces

  • Two Raspberry Pi Hat 40-pin connectors

  • Arduino Shield

  • Two MikroClick interfaces

  • HSIO interface, which is compatible with some SYZYGY interfaces

  • USB UART and JTAG

  • Ethernet

  • Switches (DIP and push-button)

  • LEDs

  • 128 Mb of configuration RAM

  • 64 Mb of HyperRAM

The SCU35 is an interesting development board to get started with and comes with a plethora of interfacing solutions.

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First Project: UART-Controlled LED PWM

One of the main applications will, of course, be deploying MicroBlaze V devices within the SCU35P to provide communication interfacing and configure the processing chains within the solution.


To get started with the SCU35 board, I thought I would implement a simple design which uses RS232 commands sent over a UART to access and control a PWM to the LEDs. This is a nice and simple example which enables us to understand working with the device, constraining, and, of course, the resource allocation.


The application is a pure RTL one and uses an adaptation of the code used in my Hackster project. You can see a block diagram below of the implementation.

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Compact Logic Footprint and Debugging

When it comes to utilisation, this design has a small, compact logic footprint. This includes an ILA I inserted to aid debugging if necessary.

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Python and Jupyter Integration

We can also leverage the power of Jupyter and Python and create a simple notebook which will send commands over USB to set and read the PWM value.

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Looking Ahead

I think the Spartan UltraScale+ is going to be a very popular device. Going forward, we have several projects in mind for it, both on the SCU35 and the device itself. One thing we have started looking at is the concept for a Spartan UltraScale+ tile to complement our Spartan Tile, the concept for which is below and contains a couple of new additions.

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I have uploaded the project to my GitHub.


You are going to see a lot more blogs and projects in the coming weeks and months based around this range.


UK FPGA Conference

FPGA Horizons - October 7th 2025 - THE FPGA Conference, find out more here.


Workshops and Webinars:

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Boards

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  • Adiuvo Embedded System Development board - Embedded System Development Board

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Embedded System Book   

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