One of the things I have been examining lately is how I can leverage higher-performing devices, such as the Spartan UltraScale+, to implement more compact FPGA designs. There are several approaches we can take to achieve this based on the higher performance of the logic. For example, we can run AXI buses narrower but at a higher frequency; in this case we leverage the increased performance of the fabric. This works well for interfaces around our module, although the core of t

Recently, I have been doing a lot of work with the SCU35 and the Spartan UltraScale+ FPGA it features. Much of this work revolves around...

The Spartan UltraScale+ family is designed to provide developers at the edge with a wide range of interfacing solutions, coupled with...