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MicroZed Chronicles: Lessons from bringing up Ethernet.

Over the past few weeks, I have been bringing up Ethernet on several different custom Kria systems. Each design utilized multiple GEMs (Gigabit Ethernet MACs), with implementations ranging from RGMII connected directly to the PS MIO, SGMII via the PS GTR, and MII/RGMII through EMIO using the programmable logic.

Some of these bring-ups were more straightforward than others, and I thought it would be useful to share the lessons I — and hopefully the clients — have learned.

 

There are two different and important aspects of brining the Ethernet up, the first is to demonstrate the underlaying hardware and connections are functional. This can be called hardware verification, once we have retired the risk of a hardware error the next step is to implement the interface as required by the user requirements e.g. using embedded Linux in place of an LWIP Echo Server.

 

The difference is important as it allows us retire risk in the hardware, releasing the hardware for manufacture.

 

Regardless of which Media Independent Interface (MII) your application uses, it is essential to plan for Ethernet from day one. Here are the key lessons:

 

Enable JTAG Boot Mode

Ensure your board's configuration mode can be set to boot from JTAG. This allows you to easily run bare-metal applications on the board, such as the Lightweight IP (LWIP) stack. Tools like the LWIP Echo Server are incredibly helpful for initial Ethernet interface bring-up, as they eliminate many of the abstraction layers involved with U-Boot or PetaLinux.

 

Provide Correct Clocks

When using SGMII, clocks are often supplied by an external oscillator — ideally one that is programmable over I2C. Make sure the clock is correctly programmed, and that NVRAM settings (if applicable) are properly configured. Tip: If possible, route a spare clock output to a test point. This allows easy probing to verify the clock frequency before starting bring-up.

 

Manage PHY Reset Properly

The PHY configures itself based on the strap pins at the moment of reset release. It is crucial to ensure the reset is asserted and held for the correct duration. When working with PetaLinux, you can define the reset MIO or EMIO pin in the hardware design, and configure the reset behaviour and duration in the device tree

 

Define an Accurate Device Tree

For embedded Linux solutions, ensure that the Device Tree accurately describes:

  • The reset pin and its timing

  • The PHY address (set by strapping)

  • The MAC address

  • The PHY mode (SGMII, RGMII, etc.)

  • The compatible PHY driver

Small errors here can make bring-up very painful – but you know it is working at the hardware level from your earlier risk retirement.

 

Example device trees for SGMII can be seen below, change the PHY address in red to the address of your PHY. In this application the PS MIO GPIO73 is used as the reset.

#include <dt-bindings/phy/phy.h>
/include/ "system-conf.dtsi"
/ {
};

&gem0 {
    status = "okay";
    phy-handle = <&phy0>;
    phy-mode = "sgmii";
    local-mac-address = [12 34 56 79 ab cd];
    pinctrl-names = "default";
    mdio {
        phy0: phy@<PHY address> {
            compatible = "ethernet-phy-id2000.a231";
            reg = <PHY address>;
            reset-gpios = <&gpio 73 GPIO_ACTIVE_LOW>;
			ti,dp83867-rxctrl-strap-quirk;
			ti,fifo-depth = <0x01>;
			reset-assert-us = <1000>;
			reset-deassert-us = <1000>;
        };
    };
};

 

Use ethtool for Diagnostics

Including ethtool in your Linux build can be invaluable. It allows you to inspect the link status, packet types received, link speed, duplex mode, and much more for interfaces like eth0, eth1, etc. This greatly aids troubleshooting during bring-up and validation.

 

Performance Testing

Even once the Ethernet interface is operational, validation isn’t complete. It’s critical to verify that the interface delivers the required performance. Using tools like iperf (available within PetaLinux) can help you benchmark throughput. Remember, external network conditions — such as cabling and switches — can significantly impact your test results, so ensure you control the test environment carefully.

 

Some application notes which might be of help include

 

Answer record 66592  - SGMII using PSGTR.


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