MicroZed Chronicles: Spartan UltraScale+ SCU35, Resources
- Apr 15
- 4 min read
FPGA Conferences
One of the most exciting FPGA families at the moment is the Spartan UltraScale+. These devices combine UltraScale+ fabric with advanced features such as support for post-quantum cryptography, high-speed transceivers, and XP5IO for DDR5 support in the larger devices. This makes them an excellent choice for developers seeking a balance of performance, capability, and cost.
To enable developers to get hands-on with the Spartan UltraScale+, AMD has developed the SCU35 development board. This board features the SPU35 FPGA combined with a wide range of interfaces, including Pmod, HSIO, Raspberry Pi (RPI), Click, and standard UART and Ethernet interfaces.
Several targeted reference designs (TRDs) are available to help developers get started:
Technical Reference Design (TRD) – This design uses the interfaces on the SCU35 board and runs under the control of a MicroBlaze V processor. It enables users to test board interfaces including Pmod, LEDs, push buttons, current sensors, and the accelerometer.
https://docs.amd.com/r/en-US/xd333-scu35-trd-instructions/Run-the-TRD
Data Acquisition Targeted Reference Design – This TRD demonstrates how developers can expand system I/O using high-performance peripherals. It shows how the SCU35 and its HSIO can be used to sample high data-rate analogue signals and provide them to a Raspberry Pi for further analysis and use. Connected over SPI, this same approach can be applied to any processor requiring I/O expansion.
Environmental Design Targeted Reference Design – This TRD demonstrates the creation of an environmental monitoring system. Such health and usage monitoring is commonly used to ensure that a system operates within acceptable environmental limits. The design uses a MicroBlaze V processor connected to several peripherals to monitor humidity, temperature, remote temperature via a thermocouple, and ambient light. An RTC is also provided to generate timestamps, while communication is achieved using a Click Ethernet module. This demonstrates how Ethernet communication can be implemented using a simple SPI-based solution, enabling the application to be contained entirely within internal BRAM.
https://docs.amd.com/r/en-US/xd346-scu35-environmental-design-trd
Zephyr RTOS I/O Targeted Reference Design – This TRD makes all of the SCU35 board interfaces available to the developer using the Zephyr RTOS. It exposes interfaces such as I2C, Pmod, UARTs, RGB LED, Click, and push buttons. This provides an excellent starting point and reference for developers looking to use Zephyr with the SCU35 platform.
Beyond reference designs, the Spartan UltraScale+ also enables developers to take advantage of its higher performance fabric to implement more advanced design techniques.
One such technique is logic folding, which allows designers to reduce logic utilisation by time-multiplexing operations across fewer hardware resources, leveraging the higher clock frequencies achievable in UltraScale+ devices. Logic folding is a technique that all FPGA engineers should be familiar with. A complete demonstration and walkthrough can be found in Issue 2 of the FPGA Horizons Journal.
Another technique developers can use to leverage Spartan UltraScale+ devices is RAM double pumping. This involves running BRAM at a multiple of the clock frequency used for the rest of the processing core, effectively increasing memory bandwidth without requiring additional memory resources. A full worked example of RAM double pumping can be found here.
While these resources are targeted at Spartan UltraScale+ devices, the techniques and approaches discussed can also be applied across other AMD FPGA families, including the Artix UltraScale+ range.
FPGA Conference
FPGA Horizons US East - April 28th, 29th 2026 - THE FPGA Conference, find out more and get Tickets here.
FPGA Journal
Read about cutting edge FPGA developments, in the FPGA Horizons Journal or contribute an article.
Workshops and Webinars:
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include:
Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal
Professional PYNQ Learn how to use PYNQ in your developments
Introduction to Vivado learn how to use AMD Vivado
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux
Arty Z7-20 Class looking at HW, SW and PetaLinux
Mastering MicroBlaze learn how to create MicroBlaze solutions
HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with PetaLinux OS
Boards
Get an Adiuvo development board:
Adiuvo Embedded System Development board - Embedded System Development Board
Adiuvo Embedded System Tile - Low Risk way to add a FPGA to your design.
SpaceWire CODEC - SpaceWire CODEC, digital download, AXIS Interfaces
SpaceWire RMAP Initiator - SpaceWire RMAP Initiator, digital download, AXIS & AXI4 Interfaces
SpaceWire RMAP Target - SpaceWire Target, digital download, AXI4 and AXIS Interfaces
Embedded System Book
Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here. Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.
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