MicroZed Chronicles: Looking Beyond the FFT

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here.

The $99 Artix UltraScale+ Explorer Board - learn more here

Over the last few blogs we have been looking at element of DSP and signal processing, especially elements which allow us to work in the frequency domain such as Filters and Fourier Transforms.

I have also been experimenting a little recently with the Opal Kelly XEM7320,and FrontPanel which is very interesting for visualisation.

So using the XEM7320 fitted with a SYZYGY SZG-ADC pod containing a LTC2264-12 dual channel ADC. I thought it would be good to create an example which allows us to understand how we can extract more information from the frequency domain.

To do this I created the ADC interface in RTL, connected it through an FFT to the FrontPanel IP core, and developed a FrontPanel application on the host to pull out the results of the FFT.

In this blog I want to step back a little from implementation detail and focus on what we do with those FFT frames once we have them, because how we present spectral data matters just as much as how we capture it.

I will make the Vivado design, IP cores, and FrontPanel App available on my GitHub if you a want to examine them in more detail.

The Limitation of a Single Spectrum

As we have seen the FFT is one of the key elements of FPGA signal processing. To use it we give it a block of samples and the result tells us the amplitude present at each frequency across the first Nyquist zone. In the example I created we are sampling at 40 MS/s with a 4096 point FFT in the fabric, which gives me a bin resolution of 9.766 kHz across DC to 20 MHz.

The problem is that a single FFT frame is a snapshot taken at one point in time, it does not contain any history.

The FFT output tells us what the spectrum looked like during one 102.4 microsecond window and nothing more. If the signal environment is stationary, a sine wave sitting at a fixed frequency for example, a snapshot is perfectly adequate, and indeed it is exactly what we use for ADC dynamic testing where we compute SNR, SFDR and ENOB from a coherent capture.

Real signal environments are rarely that accommodating however, signals sweep, hop, pulse on and off, and change amplitude. Interference arrives, misbehaves for a few milliseconds and disappears again. A spur may be present in one capture and absent in the next, and with a single spectrum we have no way of knowing whether if we saw a persistent problem or a one-off event. Anyone who has chased an intermittent EMC issue with a spectrum analyser in single sweep mode will know this frustration.

We can seethe history of the FFT frame by using a waterfall display this by adding the missing dimension, time. Each FFT frame becomes one row of an image, frequency runs along the horizontal axis, capture order runs down the vertical axis, and amplitude in dBFS is mapped to colour. The spectrum stops being a photograph and becomes a film, and entire classes of behaviour that are invisible in a snapshot become more visible.

The System Behind the Display

Before looking at the waterfall diagram let me first explain the design in the XEM7320 FPGA. The RTL interface to the ADC handles the LTC2264-12 in its default two lane, 16 bit serialisation mode. The pod returns a 160 MHz DCO alongside the serial data, giving a bit rate of 320 Mbit/s per lane, in the Artix-7 I use the SelectIO 8:1 DDR to perform the deserialisation.

The ADC IP core then detects the frame pattern rotation, aligns all lanes to the same sample boundary, reconstructs the 12 bit samples and presents both channels as a 32 bit AXI4-Stream master through a small asynchronous FIFO.

As the ADC needs to be configured at start up / reset an SPI sequence configures and verifies the ADC. This means the interface comes up ready to stream without host involvement, simplifying integration. The configuration of the ADC over the SPI can be achieved by using generics in VHDL.

The ADC IP Core out stream is input into a 4096 point FFT, and the complex results are made available to the host through the FrontPanel IP core over a block pipe. Here we needed to create a simple AXIS to Block Pipe necessary for the FP IP Core in the FPGA.

At first I created a simple FPApp which shows the waterfall diagram as it was captured. This is useful but I wanted to be able to demonstrate why waterfall diagrams are useful. Hence I need to be able to control both the XEM7320 capture and the signal generation.

To ensure I could do this I created a python script which allows me to control both the XEM7320 and the waveform generator.

Using the same Python script ensures both stimulus and capture are coordinated as a single script performs both function.

What the Waterfall Reveals

To demonstrate why the time axis earns its keep, the python application runs three scripted scenarios, each producing a 72 row waterfall.

The first is a coherent stepped chirp from 0.25 MHz to 9 MHz. On the waterfall this appears as a clean diagonal line marching across the band, and the constant slope immediately confirms that the step sequencing and the row capture are behaving. More interesting is the second, fainter diagonal running at twice the slope. That is the second harmonic of the generated tone, and the waterfall identifies it without any analysis at all, because a harmonic must track the fundamental at an integer multiple of its trajectory. This is a genuinely powerful diagnostic technique. Different spur mechanisms trace different paths as the input moves. Harmonics run at multiples of the fundamental slope, while images and interleaving artefacts reflect about Nyquist and run with the opposite slope. A single spectrum shows you a spur; a waterfall under a swept stimulus tells you what kind of spur it is.

The second scenario is a deterministic frequency hopping sequence. Here the waterfall shows short dashes scattered across the frequency axis, each one a dwell at a pseudo random frequency. Try to characterise this signal with individual spectra and you would see a single unexplained tone in each capture, at a different frequency every time, which looks indistinguishable from intermittent interference. The waterfall makes the structure unmistakable, revealing the dwell time, the hop set and the repetition of the pattern. Frequency agility is a staple of modern communications and of the radar world I spent many years in, and the waterfall is the natural way to observe it.

The third scenario combines tone bursts separated by silence with a sequence of amplitude coded hops. The bursts appear as short vertical strokes with genuinely quiet rows between them, which also serves as a useful check on the noise floor of the capture chain when no stimulus is present. The amplitude coded section then shows the same colour scale doing double duty, with the brightness of each dwell reflecting the programmed level. Time gated behaviour of this kind, signals that switch on and off, is completely opaque to a snapshot, because the answer to what the spectrum contains genuinely depends on when you ask.

Wrapping Up

None of the three examples above can be easily described by a single FFT frame, and between them they cover a large fraction of the signals we actually encounter, whether we are verifying an ADC front end, hunting an intermittent spur, or observing a frequency agile emitter.

The waterfall costs us very little. The fabric was already producing FFT frames faster than we could use them, and the host simply has to keep the rows honest and paint them. In return it converts the FFT from an instrument that answers what is present into one that answers what is happening, and that is usually the question we actually wanted answered.

With the XEM7320 and the SYZYGY ADC pod, the whole chain from LVDS deserialisation to a live waterfall runs on a compact, low cost platform, and the FrontPanel integration means the host side is a few hundred lines of Python rather than a driver development exercise. In future blogs we will build on this foundation, as there is plenty more we can do once the spectrum has a time axis.

FPGA Conference

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here.

FPGA Journal

Read about cutting edge FPGA developments, in the FPGA Horizons Journal or contribute an article.

Workshops and Webinars:

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include:

• Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal

• Professional PYNQ Learn how to use PYNQ in your developments

• Introduction to Vivado learn how to use AMD Vivado

• Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux

• Arty Z7-20 Class looking at HW, SW and PetaLinux

• Mastering MicroBlaze  learn how to create MicroBlaze solutions

• HLS Hero Workshop  learn how to create High Level Synthesis based solutions

• Perfecting Petalinux  learn how to create and work with PetaLinux OS

Boards

Get an Adiuvo development board:

• Adiuvo Embedded System Development board - Embedded System Development Board

• Adiuvo Embedded System Tile - Low Risk way to add a FPGA to your design.

• SpaceWire CODEC - SpaceWire CODEC, digital download, AXIS Interfaces

• SpaceWire RMAP Initiator - SpaceWire RMAP Initiator,  digital download, AXIS & AXI4 Interfaces

• SpaceWire RMAP Target - SpaceWire Target, digital download, AXI4 and AXIS Interfaces

• Other Adiuvo Boards & Projects.

Embedded System Book   

Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here.  Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.

All words in this blog were written by a human.