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MicroZed Chronicles: Testing GTH Transceivers

  • 22 minutes ago
  • 7 min read

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here.

The $99 Artix UltraScale+ Explorer Board - learn more here


One of the more ambitious decisions we made on the Adiuvo Explorer board was to bring out the Artix UltraScale+ GTH transceivers. As I have explained several times one of the motivations behind the explorer board is to demonstrate we can create an effective 0.5 mm pitch BGA PCB using only through hole vias.


We have achieved this using an offset via technique on the breakout which provides sufficient clearances. This is what allows the Explorer to hit its aggressive price point, and hopefully it performance targets.


One of the targets of course was to be able to use the 12.5 Gbps GTH provided, to ensure this was possible during layout we performed a lot of signal integrity analysis on the routing and stack up.


Having worked our way through the rest of the interfaces in this blog we are going to look at how we verified the GTH links in hardware using the Integrated Bit Error Ratio Tester (IBERT), and along the way explore what bit error ratio and eye diagrams actually tell us about a serial link, not just those on the explorer board.



Breaking out a 0.5 mm pitch BGA with through hole vias is tight. There is very little room between pads, escape routing is constrained, and the via stubs and breakout geometry inevitably create small impedance discontinuities that simply cannot be avoided with this technology even when using offset via techniques.


I knew this was going to be a challenge which is why I commissioned the best post layout signal and power integrity engineer I know Dan Binnun at E3 Designers before I sent out the boards for manufacture and assembly.


This analysis imported the ODB++ into SIwave, with the connector, via and BGA regions solved in HFSS, and extracted the passive channel S-parameters from the FPGA to the connector across DC to 30 GHz.


The impedance and crosstalk scans flagged exactly what you would expect given the approach taken. Minor violations concentrated in the BGA breakout region which cannot be fixed with through hole technology. The important results are seen in the differential insertion loss and the full channel simulation. The differential insertion loss which sits at roughly 3 dB at the 6.25 GHz Nyquist frequency for 12.5 Gbps operation.


While running a full channel IBIS-AMI simulation, using the UltraScale+ GTH transmitter and receiver models concatenated with package and die S-parameters, showed a passing eye at 12.5 Gbps with comfortable margin against the GTH mask in UG1183.


The results of Dan’s analysis and simulation indicate the GTH should work at the desire line rate. However, we had to wait until the boards were in the lab before we could verify this, and this is where the IBERT IP core comes in.



IBERT IP Core is an AMD provided IP core which we can generate for the GTH quads in the design and interact with over JTAG from Vivado hardware manager.


It configures the transceivers to transmit and check pseudo random bit sequences, in our case PRBS 31-bit, which provides a demanding pattern with long run lengths and a rich spectral content that stresses the link far harder than typical protocol traffic.


For this test the four GTH lanes were placed in loopback, so each transmitter drives its paired receiver through the physical channel, exercising the real board level routing including the BGA breakout we were concerned about.


On the SYZYGY TR4 Interface I connected a SYZYGY QSFP Pod and in the QSFP Socket I inserted a loop back adapter. When I ran this on the hardware Vivado auto detected the four links, all running at 12.5 Gbps, which is the maximum line rate supported for the GTH in this package.


But it raises a question how good is the link and correspondingly how happy should I be, this is there the bit error rate and eye diagram captured by the IBERT are important.


The bit error rate is simply the number of bits received in error divided by the total number of bits transmitted.


Every link is going to have some error rate, no matter how “perfect” it is, noise sources  such as thermal noise with it long gaussian tail will ensure if we run a link for long enough an error will occur. This is why when we design a link we include error detection mechanisms to sure any errors can be accommodated and do not lead to larger issues.


We can however, identify the quality of a link by determining its bit error rate, typically for a GTH link we look for a BER of 1E-12 or better.


Running the design for a soak test shows the four links accumulated just over 2E11 bits with zero errors, giving a measured BER bound of 4.93E-12 per link.


Running the four links together, the aggregate observation exceeds 8E11 bits without a single error across the quad, which puts us comfortably on track towards demonstrating 1E-12 class performance.


One thing to note here is for this test the DFE was enabled and the transmit differential swing set to 873 mV.


There was no with no pre or post emphasis applied, which gives us some equalisation headroom in hand should a more challenging external channel require it.



The eye diagram is the classic picture of serial link health, and one we first think of when discussing serial link performance.


Conceptually we take the received waveform, slice it into unit intervals, and overlay thousands of these slices on top of one another. The result resembles an eye: the open region in the centre is where the receiver can reliably sample the data, while the closure at the edges represents the combined effects of inter symbol interference, jitter, crosstalk and noise. The wider and taller the opening, the more margin the link has in time and voltage.


Here is the crucial point though, at 12.5 Gbps, if we probed the differential pair at the receiver pins with an oscilloscope, we would very likely see a closed eye.


The channel loss and ISI at these rates close the eye before it ever reaches the device, this is entirely expected, because the receiver does not make its decision at the pins.


The signal first passes through the receiver's analogue front end and equalisation stages, the Continuous Time Linear Equaliser and in our case the DFE, which reopen the eye before it reaches the sampler.


The only eye that matters is the one at the decision point, after equalisation, and the only way to see that eye is to measure it inside the device.


This is exactly what the IBERT eye scan does. The GTH receiver contains an additional offset sampler which can be swept in both time, across the unit interval, and voltage, relative to the data sampler.


At each offset point the hardware compares the offset sample against the actual received data and counts disagreements, building up a two dimensional BER map, which is what the statistical eye below actually is.


Each contour represents a BER level, with the blue central region corresponding to a BER of 1E-6 or better at this scan depth.



The scan on our loopback channel shows a wide open eye with an open area of 3776 codes and an open UI of 55.56 percent.


Given the channel includes two traversals of the 0.5 mm BGA breakout that the SI analysis flagged as the weak point of the through hole approach, this is a very satisfying correlation between the pre fabrication simulation and the measured hardware.


IBERT proves the physical layer, but of course I wanted to see an actual application running on the hardware.


The next step was to create an Aurora 64B/66B loopback design, again running the GTH at 12.5 Gbps.


Here I used an ILA to show the channel / lane status and the looping back of the aurora data which was just a simple count.  



My final test was to see how the board would work when connected to third party equipment. And contains a sneak peek of a up coming article.


I connected the Explorer containing an as yet unreleased SDR design, to an Exostiv probe.



The design uses a high speed ADC on the standard SYZYGY port, I connected the debug probes to the received data from the ADC in the FGPA.


I used all four GTH lanes to connect to the probe at12.5Gbps, giving 50 Gbps of aggregate capture bandwidth out of the FPGA, again at the package maximum line rate.


The probe detected the link, validated the IP and completed captures without issue, which demonstrates the transceivers running a sustained, real world workload rather than just test patterns.



The takeaway from this testing is twofold, first the IBERT gives us everything we need to characterise a serial link in system. It provides us a statistical demonstration of BER using PRBS patterns, and a post equalisation eye scan measured at the only point in the system where the eye is meaningful, the receiver decision point.


The second point is that careful SI analysis up front means that even a 0.5 mm pitch BGA broken out with standard through hole vias can support 12.5 Gbps serial links with real margin, keeping the Explorer board affordable without compromising its capability.


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