FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here A few weeks ago we looked at implementing a DFT from scratch as part of the labs for the DSP for FPGA course I am developing. The DFT worked nicely; however, we finished by noting that it does not scale well. For a DFT of size N, we need N² complex multiplications, which means a 1024-point DFT requires over a million of them. This is where the Fast Fou

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here. The $99 Artix UltraScale+ Explorer Board - learn more here One of the things I am working on is a DSP for FPGA course which takes you from initial concepts through to hands on examples and labs. As part of this I wanted to generate simple labs for the students which allow them to build filters, DFTs and FFTs themselves. Even though in reality we might just drop in an IP core in the interest of time, I think it

FPGAs are great for implementing signal-processing functions such as FIR filters. The DSP elements, with their built-in multiply–accumulate capability, are ideally suited for this application. However, as with most things in FPGA design, the achievable performance depends heavily on how we architect the implementation. At a basic level, a FIR filter consists of three main elements: A delay line Multipliers to apply the coefficients An accumulator to sum the products Exactly h

Recently I was talking to a good friend of mine and he mentioned that a lot of the FPGA engineers he was talking to lacked DSP...

In last weeks blog, we looked at one of the most important algorithms ever developed: the FFT. In this week’s blog, we’ll be discussing...