The great thing about FPGAs is that they allow us to create very efficient interfaces for a range of applications. I recently came across a project where I wanted to write an eINK / ePaper to display information. These interfaces are pretty straight forward and use a SPI interface, data or command bit, and reset as well as provide a busy indication for when a command is being processed.
If you wanted to implement it within a FPGA, a common approach is to use a microprocessor like the MicroBlaze to configure the information. In many cases, however, a microprocessor is over kill. These displays are not updated often but they can be used to provide persistent information like showing information on the display even when the power is removed. They can be used for a range of applications and usages include electronic serial numbers and displaying build / version information on systems remotely deployed, just to name a few.
In this blog we are going to look at how we can create a simple ePaper display which is implemented using only logic and Block RAMS.
The module will have the following simple requirements:
It shall be implemented using programmable logic.
It shall implement a SPI mode 0 interface capable of clock rates of up to 1 MHz.
It shall be capable of indicating if the SPI byte is a data (1) or command (0).
The module shall receive a busy signal to indicate the ePapers ability to process data.
The module shall provide a power up reset of 10 mS.
The module shall be capable of displaying up to 40,000 pixels.
The module should be able to provide a flexible pixel range.
The module pixels values shall be stored in an external BRAM.
The module shall perform configuration of the eINK following power on reset.
When we look at the architecture of the module, we can define the following architecture.
The SPI element is the simpler of the two to create and we are going to use three VHDL processes to create the implementation. The first process will create an internal SCLK at the desired frequency. This counter will free run, but be synchronised each time the data is loaded for transmission.
The main component of the SPI element is a state machine which loads the output serial register, and waits for the serial shift register to complete clocking out the byte of data. The SPI state machine can be seen below.
The final process loads in the data byte and shifts it out in a manner compliant with SPI mode 0 to ensure the receiver is able to sample on the rising edge of SCLK. This means we change the data output on the falling edge of SCLK to provide the optimal margin.
Within the ePaper module, we implement a complex state machine which is able to perform the following:
Pre-configuring the ePaper display, enabling the voltages, defining the pixel locations, loading in the refresh waveforms
Read the 5000 Bytes for the display from the BRAM block for the display pattern
Post configure the ePaper and execute operation to update the display
To store the pre-configuration and post-configuration data, I store the commands in an array with a separate array of the same size which shows if the command array byte is data or command. I use a similar approach to define the ePaper drive waveforms.
This allows a FSM to be created which then can interact with the SPI function and cycle through the command and the Block RAM display.
Once these have been created, we can create a test bench and double check that the output data is what we expect.
I have put the test bench and code for this design on my GitHub if you want to take a look. We are going to look at how we can prototype this on hardware using an Arty Z7 in the next blog.
This IP block will provide the ability to update the ePaper display during run time by updating the RAM contents or having a fixed unchanging display using a COE file to configure the BRAM during buit stream generation.
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