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MicroZed Chronicles: RFSoC and RFSoMs

Some of my most interesting professional developments have involved using high-sampling-rate ADCs and DACs with FPGAs. The FPGA is a natural partner for communications, RADAR, and electronic warfare (EW) systems, all of which rely on ADCs and DACs operating at giga-samples per second (GSPS).


The RFSoC range combines giga-sample ADCs and DACs with high-performance programmable logic and processor engines. First introduced in 2018, we have examined RFSoC devices, particularly the ZCU111, several times throughout this series.


These devices have proved incredibly popular, leading to second- and third-generation devices with increased sampling rates, as well as the introduction of the Digital Front End (DFE) RFSoC range. The DFE devices incorporate additional hard silicon blocks specifically targeted at RF applications.



These hard blocks include channel and equalisation filters, FFTs, nonlinear processing blocks, mixers, and other functions commonly implemented in 5G and OpenRAN solutions. The use of hard blocks not only increases performance, but also significantly reduces latency and power consumption while freeing up programmable logic resources for user-defined functionality.


In this blog, we are going to take a look at an RFSoC System-on-Module (SoM): the KRM-2ZV67DR from Knowledge Resources.



This is a compact RFSoC SoM which provides eight 2.95 GSPS ADCs, two 5.9 GSPS ADCs, and up to eight 10.0 GSPS DACs. To support high-speed data movement on and off the module, eight 32-bit GT transceivers are provided, along with 6 GB of DDR4 memory connected to the programmable logic (PL).


To test the RFSoM, we use the KRC-2000 carrier board, which provides power, RF clocking, ADC and DAC connections, and standard interfaces such as Gigabit Ethernet, USB, QSFP, and UARTs connected to both the board management controller (BMC) and the RFSoC processing system (PS).



One particularly nice feature of the KRC-2000 is the BMC, which allows control of the RFSoC power state. Using a UART interface, we can power the RFSoM up and down, configure its clocks, and select configuration modes, making development and experimentation significantly easier.



This is the first DFE-based RFSoC we have examined in the blog. To get started, we will generate a single-tone output from one of the DACs. For this example, we use a single DAC tile configured with a sampling rate just under 5 GSPS.


The RF DAC is configured to output a real signal, leveraging the built-in interpolator to place the tone generated in the programmable logic, at the correct RF frequency. Data is input into the RF DACs using AXI-Streaming interfaces, and depending on the DAC configuration, the required clock rate and number of samples per clock can vary significantly. This is one of the key considerations when developing RFSoC-based RF solutions.


For this initial example, the DAC configuration is kept deliberately simple, using a basic DDS in the PL to generate the output tone. In a future, more advanced demonstration, we will create a memory-based waveform buffer that can be loaded with arbitrary signals and streamed into the RF DAC. This will allow for more detailed performance testing and is an ideal use case for the attached PL DDR4 when large waveform buffers are required.


We will also explore capturing data from the ADCs in cooperation with the Exostiv probe.

The completed hardware design is shown below:



With the hardware design implemented, we then create a simple application in Vitis. This application is responsible for configuring, enabling, and controlling the RF DAC tile using the xRFDC API provided as part of the RFSoC platform.


The software application itself is very straightforward, and both the Vivado and Vitis designs have been uploaded to GitHub if you wish to explore them in more detail.

Running the application on the RFSoM, the generated output tone was captured using a spectrum analyser, confirming correct DAC configuration, clocking, and data-path operation.



I am a big fan of RFSoC devices as they enable highly integrated, high-performance RF solutions that would otherwise require significant external RF hardware. I am also a strong advocate of SoMs, and combining the two makes for a very compelling platform for rapid development, evaluation, and experimentation.


In future blogs, we will dive deeper into ADC capture, advanced waveform generation, and make greater use of the DFE blocks to demonstrate how these devices can be applied to real-world RF systems.


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