MicroZed Chronicles: Thoughts on the DRAM Situation

Over the last few months, it has become apparent that DRAM is increasing in price and becoming harder to source. This is especially true in the consumer market, driven in part by increased demand from AI workloads.

We tend to think of using the latest generation, which currently means DDR5 or LPDDR5.

DDR5 has some interesting architectural changes, which enable increased bandwidth, much faster transfer rates, and higher device densities. For example, DDR5 DIMMs are effectively split into two 32-bit subchannels, improving concurrency and efficiency versus the traditional single 64-bit channel approach.

However, like many things in engineering, it depends on what we are trying to do and what the right tool is for the job.

For some applications, (LP)DDR5 is obviously the correct choice. However, there are other applications where (LP)DDR4 can be advantageous.

Several DDR4 suppliers have announced EOL plans or have reduced long-term emphasis on DDR4.

However, there are also suppliers who are focused on embedded applications and committed to supplying (LP)DDR4 for 7-10 years or more to the embedded markets.

This makes these technologies a viable option for many applications, particularly where lifecycle planning, cost, and board complexity matter as much as peak bandwidth.

Let’s explore a few cases where DDR4 might be the more ideal solution.

Shallow Buffers - Often the on-chip fabric RAM is not large enough to store data packets or video frames. In this case, a shallow buffer may be implemented using external memory. High density memory is not needed, just a cost-effective external buffer that has sufficient bandwidth. In such cases, it is often more convenient to use a wide external interface, synchronized to the relatively slow internal bus clock. Matching the internal and external widths can reduce latency because it may eliminate the need for internal buffering and boundary alignment. For many applications, DDR4 is an ideal match for this requirement.

Latency - FPGAs are frequently utilized when the application requires low latency. What might come as a surprise is that DDR4 can potentially offer a latency advantage over DDR5, even while it operates at lower line rates. A useful rule of thumb for first-word of CAS latency is:

Latency (ns) = CL × 2000 / MT/s

A common DDR4 CAS latency is CL16 at 2400 MT/s, which equates to approximately 13.3 ns. Meanwhile, a DDR5 CAS latency of CL58 at 7200 MT/s equates to approximately 16.1 ns. Not a huge difference, but it might make a critical difference for your application.

Real system latency is more than CAS alone. Additional latency will be added by the memory controller and PHY, and it also depends on access patterns, scheduling, bank conflicts, page hits or misses, burst length, and other timing parameters.

Design Simplicity - One of the largest drivers of recurring and non-recurring costs associated with product development is the printed circuit board. The design and development of the PCB require placement, routing of high-speed signals, and analysis for signal and power integrity. The more complex the layout requirements, the greater the non-recurring engineering cost and the technical risk when it comes to integration and testing of the initial prototypes.

More complex layout requirements also tend to drive higher layer counts, and LP(DDR5) may require the use of more esoteric substrates and more advanced PCB fabrication technology, which can increase the recurring costs of the PCB. For these reasons, DDR4 can offer significant implementation benefits compared to DDR5, depending on device choice, speed grade, and layout constraints.

System-Level Bandwidth and Power - Another consideration is whether the memory controller interfaces to the logic or processor system for the chosen FPGA or SoC can accommodate the required system-level bandwidth and efficiency. If there are internal bottlenecks in the silicon design or IP, increasing the memory clock rate may not result in improved performance. The design of the memory controller may also be such that faster memory clock rates require the addition of soft logic resources, despite the use of hard memory controller IP. Due diligence is required to carefully review silicon and IP documentation, known issues, and errata for the device families you are evaluating for the design. Hardware verification of bandwidth and efficiency prior to architecture freeze can also be key to first time success.

The power reduction benefits of newer memory standards and hard memory controllers are obvious. What is less intuitive is that these benefits may be overshadowed by factors such as the availability of hard IP for video or signal processing, or even the power consumption required for I/O and high-speed transceiver interfaces.

Taking a system-level approach to estimating power consumption (including thermal performance) prior to architectural definition and final FPGA or SoC device selection helps engineers determine the most appropriate solution.

As engineers, one of the things we need to think about is selecting the right device or tool for the task. This is not only about selecting the right FPGA or SoC, but also the supporting memory, and system-level parameters such as performance and power consumption.

If you need the maximum bandwidth and density and can absorb the extra complexity, DDR5 or LPDDR5 may often be the right answer.

However, if you need cost-effective buffering, lower latency characteristics, or if you are not driven to select (LP)DDR5 to meet bandwidth or density requirements, (LP)DDR4 remains a very strong choice. The good news is that there are manufacturers committed to providing long-term supply.

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