MicroZed Chronicles: Chip2Chip

Recently, I’ve been looking at a project that uses Aurora to transfer data over fibre as fast as possible from one FPGA to another. The FPGA design implemented in each device is not very complicated, but achieving low-latency, end-to-end system performance is key.

This got me thinking about transferring data between FPGAs within our systems, something we often need to do. One popular method of communication between FPGAs is the Aurora protocol. Aurora enables a simple, lightweight communications link between two FPGAs using Gigabit Transceivers. Capable of operating in framed or streaming configurations, it is a very efficient way to send data between devices.

Aurora is great for sending data between devices. When I first came across it many years ago, we used it to send image data from one FPGA to another as part of a thermal-imaging solution.

However, it isn’t just a stream of data in the signal chain that we might want to share between FPGAs. What can we do if we want to share address-mapped data from one device to another?

This is where the AMD Chip2Chip IP core comes in: it enables us to transfer memory-mapped data between devices. Using it is straightforward; it presents AXI or AXI-Lite interfaces.

The transfer of data between devices can leverage either Aurora or SelectIO running in single- or double-data-rate modes.

I thought this would be an interesting IP to explore, so I created a project that leverages Block Design Containers (BDCs) to create TX and RX subsystems.

This approach provides two benefits. First, I can reuse the TX and RX BDCs in other projects as needed. Second, it means I can combine them within a single project and create a clean simulation example using the BDCs.

Let’s start by looking at the interface between devices. In this example, I’m using Aurora 64b/66b configured for a line rate of 10.3125 Gbps.

The master side of the Chip2Chip implementation presents AXI and (if enabled) AXI-Lite slave interfaces. This allows a processor within the processing system, MicroBlaze or any other AXI master, to initiate transactions via the IP core and read or write the AXI memory map within the second device.

Connecting the Chip2Chip IP to the Aurora IP is very straightforward, with connections for resets and initialisation logic, along with status signals such as channel up.

In this application, I used an AXI Traffic Generator to create traffic patterns to be written via the Chip2Chip IP.

On the slave side of the Chip2Chip IP core, I connected a simple BRAM to act as a memory-mapped target.

In both designs, the init clocks are set to 50 MHz, the AXI clock to 200 MHz, and each GT reference clock is provided at 156.25 MHz.

These BDCs can be combined in a top-level IP Integrator diagram that connects the GTs and provides the clocks using clocking primitives and/or clock simulators.

Make sure that the address maps in the master and slave Chip2Chip instances are aligned to ensure each side can correctly access the other’s memory space.

Simulating the design like this enables us to see how the IP core behaves without needing two boards connected together. Of course, it is also good practice to simulate the design to ensure the functionality is as desired.

When running the design in simulation, you will observe AXI writes taking place over the Chip2Chip link. You’ll first see the AXI writes on the master and, a little while later, see the corresponding AXI writes on the Chip2Chip slave.

I’ve put the design on my GitHub if you want to explore it in more depth.

I like this IP core because sometimes we need to connect devices, for example, in industrial applications where electrical isolation is required between modules. In such cases, fibre, Aurora, and Chip2Chip can be perfect for sharing data between devices.

UK FPGA Conference

FPGA Horizons - October 7th 2025 - THE FPGA Conference, find out more here.

Workshops and Webinars:

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include:

• Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal

• Professional PYNQ Learn how to use PYNQ in your developments

• Introduction to Vivado learn how to use AMD Vivado

• Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux

• Arty Z7-20 Class looking at HW, SW and PetaLinux

• Mastering MicroBlaze  learn how to create MicroBlaze solutions

• HLS Hero Workshop  learn how to create High Level Synthesis based solutions

• Perfecting Petalinux  learn how to create and work with PetaLinux OS

Boards

Get an Adiuvo development board:

• Adiuvo Embedded System Development board - Embedded System Development Board

• Adiuvo Embedded System Tile - Low Risk way to add a FPGA to your design.

• SpaceWire CODEC - SpaceWire CODEC, digital download, AXIS Interfaces

• SpaceWire RMAP Initiator - SpaceWire RMAP Initiator,  digital download, AXIS & AXI4 Interfaces

• SpaceWire RMAP Target - SpaceWire Target, digital download, AXI4 and AXIS Interfaces

• Other Adiuvo Boards & Projects.

Embedded System Book   

Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here.  Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.

Sponsored by AMD