AMD

I have had the Alinx VD100 Versal Edge AI platform for a little while now. A few weeks ago, I set it up in my office so that I could...

One of the great things about writing this blog (there are many) is when people as real world questions as they need help. Last week,...

I always remember when I was learning digital electronics at university, the lecturer John Rowe passing comment that a professional would...

One of the things I really enjoy is creating image processing solutions as you might notice from the projects I publish on Hackster. My...

Recently I retired my old trusty TI85 calculator and replaced it with a more modern scientific calculator, which could even run python....

I thought I would kick off 2025 with a look back at what we had achieved over the last year, it has been one of my busiest years yet and...

Normally, we clock the logic within our FPGA design using clocks either provided externally or generated internally using MMCMs, PLLs, or...

A couple of weeks ago I started exploring, fixed and floating point math and the differences between them in FPGA implementations. Of...

As many engineers are, I am a big fan of sci fi, growing up I used to watch Star Trek The Next Generation religiously every night here in...

I have written several blogs about setting up and running your own company ( P2 here ) , the software tools and IT infrastructure ...

When it comes to debugging designs the more visibility and control we have over debugging elements such as ILAs is critical.   When we...

Last week we examined how we could use the IEEE VHDL 2008 fixed and floating packages to implement a simple polynomial approximation.  ...

A short time ago I hosted a webinar which looked at how we can implement mathematics within programmable logic. In this webinar we...

When developing FPGAs there is a critical triad which needs to be achieved for the successful delivery of a project. First we need to...

Every digital / FPGA designer should be aware of clock domain crossing between asynchronous clock domains. As our devices get more and...

One of the main challenges FPGA designers face, especially those new to FPGA design is how to achieve timing closure. While it seems...

The goal of professional FPGA development is to deliver projects on quality, on time, and within budget. Achieving this, however, can be...

One of the things I enjoy is when people reach out with suggestions for blogs and projects that would help them. A recent suggestion was...

To make my blogs and demonstrations illustrative I often use captures from the graphical user interface. However, professionally as an...

Over the last few months we have been developing a tile, which contains a Spartan 7 XC7S25 and all of the supporting peripherals...