MicroZed Chronicles: VEK280

Over the past few months, we’ve explored several Versal™ AI Edge development boards, including the Trenz TE0905 and the Alinx Txxxx. Each of these boards is built around the VE2303 device, which provides 330K system logic cells, 464 DSP engines, 34 AI Engine-ML tiles, and 5 NoC ports.

For a recent AI development project, however, I needed something with significantly more capability. That led me to the VEK280, which features the largest device in the Versal AI Edge family. Its impressive resources include 1,140K system logic cells, 304 AI Engine-ML tiles, 1,312 DSP engines, and 21 NoC ports. My goal with this board is to demonstrate the AI Engine-ML’s capabilities for both AI inference and DSP applications.

Board Overview and Memory

The VEK280 offers far more interfacing flexibility than the other Versal AI Edge boards we’ve looked at so far. To support system operation and frame buffering for CIPS applications, it includes 12 GB of LPDDR4 memory, giving plenty of space for demanding designs.

Interfacing Capabilities

One of the biggest advantages of the VEK280 is the sheer variety of built-in interfaces, enabling rapid prototyping for a wide range of applications. These include:

• USB UART

• Two CAN-FD buses

• Two PL Tri-Speed Ethernet connectors

• One PS Tri-Speed Ethernet connector

• One SFP28

• HDMI v2.1 RX

• HDMI v2.1 TX

• One FMC+ with 8 GTYPs and 68 user I/O

• One PCIe Gen 4 x16

• One Pmod

This range supports everything from image processing and AI inference using the HDMI input/output, to real-time control on operational technology networks using PL Tri-Speed Ethernet. The presence of FMC+ also allows the board to be expanded with high-speed peripheral cards such as NVMe SSDs or Quad SFP+ FMC+ modules from Opsero.

Clocking Architecture

Supporting such a diverse set of interfaces requires equally flexible clocking. The VEK280 includes both fixed and programmable clock sources, covering:

• SFP

• FMC+

• PCIe

• HDMI

• IEEE 1588 (PTP)

A Renesas RC21008A097 clock generator provides the programmable sources and can be reconfigured over I²C, enabling you to tailor the board’s clocking architecture to suit your application. This flexibility is especially useful when working with high-speed serial interfaces like SFP or FMC+.

Boot Options

When it comes to booting, the VEK280 offers several options:

• USB JTAG for initial programming

• Octal SPI flash

• SD card

For demonstrations, I prefer to use the SD card after the initial bring-up phase. It provides a convenient and repeatable way to deploy applications once the design is stable.

Learning Resources

If you’re new to Versal AI Edge devices, there are some excellent Hackster.io projects created by AMD engineer Florent Werbrouck. These provide a solid foundation for getting started, covering both bare-metal and PetaLinux workflows:

• Getting Started with the Trenz TE950 

• Creating a Minimal Baremetal System

• Creating a Minimal baremetal System with DDR 

• Creating a Minimal Petalinux System 

• Creating your own custom example design

• Minimal Vitis Acceleration with AIE-ML

• AI Engine Compile and Simulate

  
  

These resources are well worth exploring alongside your own VEK280 experiments.

Closing Thoughts

The VEK280 represents a significant step up in capability for Versal AI Edge development. With its extensive logic, DSP, and AI Engine-ML resources, as well as its rich set of interfaces and flexible clocking, it’s ideally suited for complex AI inference, high-performance DSP, and real-time networking applications.

In upcoming posts, I’ll be diving into practical demonstrations on the board, showing how to leverage the AI Engine-ML for both signal processing and neural network workloads.

UK FPGA Conference

FPGA Horizons US East - April 28th, 29th 2026 - THE FPGA Conference, find out more here.

Workshops and Webinars:

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include:

• Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal

• Professional PYNQ Learn how to use PYNQ in your developments

• Introduction to Vivado learn how to use AMD Vivado

• Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux

• Arty Z7-20 Class looking at HW, SW and PetaLinux

• Mastering MicroBlaze  learn how to create MicroBlaze solutions

• HLS Hero Workshop  learn how to create High Level Synthesis based solutions

• Perfecting Petalinux  learn how to create and work with PetaLinux OS

Boards

Get an Adiuvo development board:

• Adiuvo Embedded System Development board - Embedded System Development Board

• Adiuvo Embedded System Tile - Low Risk way to add a FPGA to your design.

• SpaceWire CODEC - SpaceWire CODEC, digital download, AXIS Interfaces

• SpaceWire RMAP Initiator - SpaceWire RMAP Initiator,  digital download, AXIS & AXI4 Interfaces

• SpaceWire RMAP Target - SpaceWire Target, digital download, AXI4 and AXIS Interfaces

• Other Adiuvo Boards & Projects.

Embedded System Book   

Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here.  Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.

Sponsored by AMD