MicroZed Chronicles: Boundary Scan

Recently we have been developing numerous boards based around AMD devices from our Spartan 7 and RPI2040 based embedded system board, to the embedded system tile, the carrier card and several other customer boards which are based on Kria K26 modules.

There is always a rush to want to throw a FPGA design into the board, and we can and do develop test applications which test the functionality and interfaces of the board.

However, there is a faster way to enable us to test our hardware and that is to use the JTAG Test Access Port (TAP) and deploy a boundary scan solution on the board. Typically our main use of the JTAG TAP is to program the device and extract VIO / ILA information.

Boundary Scan is an interesting technology if you have not come across it before, boundary scan is an IEEE Standard (IEEE 1149.1 standard).

The idea is that within the FPGA a test cell built into its I/O pins, this allowing external tools to control and observe signals in this cell using the TAP. Essentially this puts all IO pins into a shift register called the data register, data can then be shifted into or out of the FPGA using the TAP.

The detailed cell used in UltraScale+ technology can be seen below.

When required the DR can be updated and the IO will be sampled or updated with the desired pattern. This allows the boundary scan program to be able to perform what is called an EXTEST (external test) which allows communication between devices / peripherals to be monitored.

The beauty if this is we can chain together multiple devices if our boards have more than one FPGA fitted.

What this means is we can develop boundary scan applications from the schematics which tests the connections between devices, checks for shorts and open circuits and can perform memory tests on volatile and none volatile memory if so desired.

If you are doing production of FPGA based board then boundary scan should be one of he tests you want to use to help prove the manufacturing / assembly aspects.

Increasingly this is something we have been looking at for testing our boards to ensure the manufacturing of the board is correct.

To be able to perform boundary scan testing on a board you need boundary scan equipment, currently we have a JTAG Live pod which can be used for Boundary scan test of boards. There exists however a range of JTAG / Boundary Scan test equipment which can be used for production test.

The key to boundary scan functionality and testing is what is called the Boundary Scan Description Language (BSDL) file, this file defines the configuration for a particular device. It is written in a VHDL like format if you decide to examine one.

When we work with AMD Devices and boundary scan there are two types of BSDL files we can use.

The first BSDL file defines the device when it is unprogrammed, and can be found here. While the second is the BSDL file which is written by Vivado once the design has been implemented.

We can write the bsdl file using the write_bsdl command in the tcl console.

This use of the programmed BSDL file enables boundary scan testing to sample IO cell values as used in the final design without impacting the operation of the design this Is often called a SAMPLE/PRELOAD test.

In the coming weeks we will be looking more at JTAG and boundary scan testing on custom boards. Especially as revision B of the embedded system spartan 7 tile have now arrived for bring up.

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