One common element to many of these applications is the ability to work with real-world signals. Often these signals are analog or RF in nature, requiring conversion between the analog and digital domains.
To do this, we need to use analog-to-digital and digital-to-analog convertors. Just like when selecting the correct FPGA for the job, we are faced with a multitude of choices when selecting the correct ADC or DAC for the application.
The first thing we need to establish is the sampling rate required in order for the signal to be converted (remember the Nyquist-Shannon sampling theorem). This will drive the converter and the FPGA selection to ensure that the speed grade, interfacing capabilities, and logic resources are suitable.
If you are not familiar with Nyquist-Shannon sampling theorem, it states that the sampling rate of the converter needs to be at least twice that of the signal being sampled. Therefore, if the engineer needs to sample a signal at 50 MHz, the sampling rate needs to be at least 100 MHz. If we fail to respect this rule, the converted signal will be aliased back upon itself and not be correctly represented.
Aliasing is not always a bad thing though. Sometimes we can use it to fold back signals into the useable bandwidth if the convertor input bandwidth is wide enough. This concept is especially important when we are working with RF signals and RF ADCs and DACs.
ADC and DAC Key Parameters
Analog-to-digital convertors are implemented by many different techniques, however, some of the most common are flash, ramp, and successive approximation.
Flash convertors are known for their speed and use a series of scaled analog comparators to compare the input voltage against a reference voltage. They then use the outputs of these comparators to determine digital code.
Ramp convertors utilize a free running counter connected to a digital-to-analog convertor. The output of the DAC is used to compare against the input voltage and when the two are equal the count is held.
Successive approximation convertors are an adaption of ramp convertors and also utilize a DAC and a comparator against the analog input however, instead of counting up the SAR converter determines if the analogue representation of the count is above or below the input signal. This allows a trial and error-based approach to determining the digital code.
While digital-to-analogue convertors are also provided in several different implementations, some of the most common are binary weighted, R-2R ladder and pulse width modulation.
Binary weighted is one of the fastest DAC architectures and sums the result of individual conversions for each logic bit. For example, a resistor based one will switch on or out resistors depending upon the current code.
R-2R ladder converters use a structure of cascaded resistors of value R- 2R. Due to the ease with which precision resistors can be produced and matched, these are more accurate than the binary weighted approach.
Pulse width modulation is the simplest type of DAC which passes the PWM waveform through a simple low pass analog filter. This is commonly used in motor control but also forms the basis for delta sigma converters.
The other technique which can be used to implement ADCs and DACs is called the Delta Sigma technique. Delta Sigma converters are often called single-bit convertors because they use delta modulation, the average of the level of the delta modulation represents the input signal.
Each of these has pros and cons relating to the speed of conversion, accuracy, and resolution of the conversion. Just like when selecting a FPGA, we will look at the number of IO, IO standards, clock management, logic resources and memory etc. The following similar parameters are used to compare the performance of ADCs:
Maximum sampling rate
Signal to noise ratio (SNR)
Spurious free dynamic range (SFDR)
Effective number of bits (ENOB)
The sampling frequency is simple and is basically the maximum rate at which the converter can sample its input. SNR represents the quantization noise. This is assumed to be uncorrelated with the input signal and can be theoretically determined using the equation.
SNR = 6.02N + 1.76 dB Where N is the resolution.
The actual SNR can be determined during system test by taking a FFT of the output and measuring between the value of the input signal and the noise floor.
The SFDR is the ratio between the input signal and the next highest peak. This is usually a harmonic of the fundamental. Normally the SFDR is given in terms of dBc and will degrade as the input signal power reduces. From the measurements of the convertor, the engineer can calculate the effective number of bits using the following equation:
ENOB = (SNR – 1.77 / 6.02)
When performing this testing, the engineer must take care to ensure that the FFT used is correctly sized to ensure that the noise floor shown is correct and not inadvertently incorrect due to the size of the FFT selected. The FFT noise floor is given by the following:
FFT Noise Floor = 6.02N + 1.76 dB + 10 LOG10(FFT Size / 2)
These tests should be performed using a single tone test which is normally a simple sine wave to reduce the complexity of the output spectrum. Performing coherent samples of the output is a must to get the best results. Coherent sampling occurs when there are an integer number of cycles within the data window:
FS / Fin = Ncycles / FFT
The Frequency Spectrum
As mentioned above, we must be aware of the Nyquist-Shannon sampling theorem criteria when implementing the system to ensure the signal is correctly converted or quantized. This means that the signal must be sampled at least twice the maximum frequency of the signal of interest to ensure correct conversion. Aliasing will occur when signals are sampled outside of this criterion and can result in unwanted performance if it is not correctly understood. It is also for this reason that ADCs require anti-aliasing filters to prevent signals or noise being aliased back into the quantized signal. However, aliasing can be very useful especially if the converter has a wide input bandwidth. With careful consideration, this can allow the direct conversion of signals without the need for down converters. For this reason, the frequency spectrum is divided up into a number of zones.
Nyquest Zones and Aliasing
By using the information in the table, it is possible to alias signals from one Nyquest band to another if the converter has a wide enough bandwidth.
As with all external devices, ADC and DAC interfaces are provided in several different interfacing options. The most common differentiation is the interface being either parallel or serial. Typically, higher speed devices will implement a parallel interface, while slower speed devices will utilize a serial interface. However, your choice of application may drive the engineer down a particular route. For instance, it’s easier to detect a stuck at bit in a serial interface than it is in a parallel one. Really high-speed interfaces provide multiple output buses (I and Q) or use double data rate outputs. Some devices might even offer both options. This allows the data rate to be maintained while reducing the frequency of the operation required for the interface. For example, an interface sampling at 600 MHz will produce an output at 300 MHz (half the sampling frequency). It is much easier to recover if the clock frequency is 75 MHz (FS/4) and there are two data buses which provide the samples from the device using double data rate (DDR). This allows the relaxation of the input timings required to be achieved by the FPGA engineer. Other interfacing standards used for high-speed converters leverage gigabit serial links and use the JESD204B standard. This enables much simpler interfaces because more data can be sent down fewer lines so the board layout is simplified.
Most DACs will hold the analog output until the next sampling period and allows us to observe an interesting effect upon the output frequency domain. We will notice both images existing across the output spectrum and the output signal in the first Nyquest zone exhibiting a roll off due to the Sinc effect being nearly 4 dB (3.92 dB) lower at 0.5 FS. The solution to both issues is to utilize filters. The first filter can be implemented digitally within the FPGA before the DAC and can correct for the roll off using a simple digital filter. The anti-image filter needs to be located after the DAC output because the images are a function of the conversion.
The Sinc correction filter can be implemented very simply as a FIR filter. The simplest method for the engineer to undertake in developing this filter is to plot the Sinc roll off using the following equation:
Create the correction factor which is the reciprocal of those calculated for the roll off. Then take an inverse Fourier transform to obtain the coefficients needed to implement the filter. Typically, this filter can be implemented with a few taps has shown below.
Uncorrected DAC Roll off between 0 and FS
DAC Roll Off and Compensation Filter to FS/2
Of course, this just scratches the surface of working with ADCs and DACs but at least now we are able to understand some of the key parameters which can help us when we want to implement solutions based upon them.
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