MicroZed Chronicles: Tria AUBoard 15P FPGA Development Kit

One of the great things about the FPGA world is the range of different development boards available to us. This diverse selection enables engineers to pick a development board with the device that will be on their custom solution and start development early, reducing the technical risk.

One device family which I find exciting these days is the AMD Artix™ UltraScale+™ FPGAs. We’ve had a glimpse of its potential when we explored AMD MicroBlaze™ processor optimizations using the Opal Kelly XEM8320 platform. And now Tria Technologies, an Avnet company, has released the AUBoard, which contains an AMD Artix UltraScale+ AU15P device.

Let’s first look at the key differences between the AMD Artix 7 FPGA and Artix UltraScale+ FPGA such that we can understand how to best to leverage the Artix UltraScale+ device in our designs.

Parameter	AMD Artix 7 FPGA	AMD Artix UltraScale+ FPGA
Process Tech	28 nm	16 nm FinFet
FPGA Architecture	7 Series	UltraScale+
Transceiver	6.6 Gbps GTP	16.3 Gbps GTY / GTH

The AU15P device fitted to the AUBoard provides developers with 170K logic cells, 576 DSP Slices, 7.6 Mb of BRAM and 12 transceivers.

The AU15P IO is connected to a range of interfaces and memories, including:

• 2GB DDR4

• 512 Mb QSPI

• FMC LPC

• 10/100 Ethernet

• HDMI Tx and Rx

• SFP+

• PCIe Gen 4 x4

• LEDs, switches and click interface

• 300 MHz system clock

• Clock generator for SFP+ and HDMI

Users are able to add a range of sensor modalities using the LPC count FMC from ADCs and DAC to image sensors. The PCIe and SFP+ also provide the user with the ability to get data on and off chip easily. The 10/100 Ethernet can also be used for control and configurating the processing stages on the AUBoard.

This provides us with a development board that is ideal for prototyping a range of applications, such as image and signal processing across a range of industries  - industrial, medical, networking, aerospace & defence, and AV broadcast, to name a few.

To use the board in the AMD Vivado™ Design Suite, we can download the board definition from the Avnet Board Git Store. Update the settings in Vivado to scan the downloaded board directory on start up. This will enable you to create a project targeting the AUBoard.

As part of the project creation process, we are then able to select the AUBoard from the Avnet-Tria drop down.

For this example, I am going to create a simple AMD MicroBlaze V processor design, which uses the DDR4 and 10/100 Ethernet so we can run a lightweight IP echo server.

To get started from the board tab within Vivado, add in the DDR4 SDRAM, Ethernet PHY, System UART and FPGA Reset. Once these have been added to the IP Integrator diagram, add in a MicroBlaze V configured as a microcontroller and an AXI Timer.

The final block diagram should look like the image below – the project is available on my github here.

To ensure the best performance, I used the DDR4 UI clock, which is a 300 MHz clock provided by the DDR4 MIG to clock the MicroBlaze V processor and associated peripherals. This will mean the AXI data bus between the DDR is 256 bits, which is a ratio of 4:1 of the 32 bit DDR4 Interface running at 1200 MHz.  

Once the bit stream is available, we are able to open the hardware manager in Vivado and configure the FPGA. Within hardware manager, we are then able to see the DDR4 memory calibrated and ready for use without the software application. The DDR4 MIG provides detailed information on the DDR4 MIG status and its calibration.

The final step of the test application is the development of the LWIP echo server. To do this within the AMDs Vitis™ development platform, we need to first create the platform using the XSA exported from Vivado.

Once the platform is completed, the next step is to enable the LWIP library within the platform BSP just generated.

With that completed, we are able to create a new LWIP Echo server example from the Example Applications tab.

Once this is compiled, we can run the application on the AUBoard with an Ethernet cable connected to the development PC. The echo server started as expected.

With this up and running, we have a nice demonstration of several of the key features of the AUBoard and the AMD Artix UltraScale+ FPGA. I want to explore the PCIe interface on this board so I will be creating a Hackster.io project which uses this soon.

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Workshops and Webinars:

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include:

• Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal

• Professional PYNQ Learn how to use PYNQ in your developments

• Introduction to Vivado learn how to use AMD Vivado

• Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux

• Arty Z7-20 Class looking at HW, SW and PetaLinux

• Mastering MicroBlaze  learn how to create MicroBlaze solutions

• HLS Hero Workshop  learn how to create High Level Synthesis based solutions

• Perfecting Petalinux  learn how to create and work with PetaLinux OS

Boards

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• Adiuvo Embedded System Development board - Embedded System Development Board

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