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MicroZed Chronicles: Vitis Heterogeneous System Design

One of the changes to tooling I have not written about to much is the Vitis Unifieds ability to create heterogeneous system designs, our focus to date has been looking at embedded flow.

 

However, Vitis Unified provides a much wider capabilities which are needed when working with Versal, MPSoC, Kria SoM and Alveo designs.

 

Along side the traditional embedded software development, Vitis unified allows us to generate system solutions which pulls together

 

  • Embedded software

  • Programmable Logic Kernels developed using either HLS or RTL (in Vivado)

  • AI Engine graph design

 

What this really means is that when developing in Vitis using the heterogeneous system development we are able to pull together a diverse range of resources for our solution and package into system solution.

 

The output of the heterogeneous system design compilation provides a SD Card image. What is on the SD Card varies a little depending on the target device for the UltraScale+ MPSoC and Kria SoMs the output format is a XCLBin, while for Versal designs it is as fixed platform (XSA), I will describe exactly what this is below.

 

If we are working with a custom Versal platform we can export the Vitis design into a Vitis Metadata Archive (VMA) and re import it into Vivado for further analysis.

 

Both of these flows us Vivado under the hood and as we get more comfortable using the Vitis heterogeneous system design approach we can also work manually with Vivado during different stages of the implementation to enable customisation if desired.

 

To be able to effectively work with the Vitis Heterogeneous System Design flow there are some key concepts we need to understand.

 

Extensible Platform – This is a target platform for Vitis System Design Flow. It is called extensible as it can be extended by the addition of PL kernels or AI Graph applications.

 

Fixed Platform – This includes a completed hardware design and supporting software files e.g. OS, Libraries and Boot files.

 

Kernel Image – This is the embedded Linux kernel image which will be running on the Kria SoM, UltraScale+ MPSoC or Kria SoM

 

PS Application – The software application which runs on the arm cores and controls and interacts with the PL Kernels and AI Engines.

 

RootFS – This is the Root File System which is mounted by the embedded Linux Kernel.

 

SysRoot – This is a reduced of the filesystem (RootFS), it only contains the libraries and headers which can be compiled and linked against.

 

Vitis Compiler – The V++ compiler which is able to compile PL Kernels and links the PL kernels and AI Graphs to build the device.

 

XRT – Xilinx Run Time Library – This is an API and associated drivers which allow data and stats transfer between the OS and the hardware design which contains the PL kernels and AI Graph.

 

Xilinx Support Archive – This is the hardware container exported from Vivado

 

The Heterogeneous System design flow is based around PetaLinux, as such we need to be able to provide the Kernel Image, Roots FS and SysRoot also to Vitis.

 

We also need to develop the solution using a Linux machine or virtual machine, in my case I am using a Ubuntu 22.04 LTS. 

 

To help us get started on this development flow AMD helpfully provide us with a common images, sysroots, rootfs and extensible platforms for a range of Versal and UltraScale+ MPSoC Targets.  You can download these from the AMD Downloads page here.

 

One of the things I want to do is explore this flow in detail looking at the custom platform creation and integrating PL kernels. However, to wrap up this blog we will look at creating the simple example of a vector add.

 

The first thing we need to do is download the common images, within the common images once downloaded we will find the kernel image, rootfs and a script sdk.sh which we can run to build the sysroot.

The first thing we need to do is to build the sys root, we can do this by running sdk.sh this will take a few minutes then result in the SDK being made available.

The next thing we need to do in Vitis is create a new system design project from the included examples.

Name the project and select the location.

For this example I am going to select the ZCU104 as the target board.

Provide the paths to the image, sysroot and rootfs.

Click finish

This will open the Vitis Example System Design example which is based around vector addition.

 

In the Vitis Explorer you will see three elements, the at the top is the overall application and contains all of the settings for the overall application. This is followed by the host application which runs on the processor cores and is a traditional embedded SW application. Except that is provides data too and configures and controls the kernel in the PL. This is defined by the final element which is the PL kernel defined in HLS.

This example includes everything we need to build the application, in 2024.2 there are two main paths to build the application.

 

The first is Hardware emulation, this processes uses Qemu, and Vivado simulator to co simulate the design as created. While the second is to build the deployable image, for this blog I did both.

 

First I built the System Design targeting hardware emulation, I was the enable to start the emulator, run the application and as I said I wanted to record the waveform Vivado simulator was opened to enable exploration of the waveforms.

Once I was happy the hardware emulation would build and the tests passed, I built the deployable hardware.

This gives the complete SD card image to boot on my ZCU104 board. Of course, at the end of the compilation process it provides a number of reports which detail implementation details.




It has been a while since I looked at the system design flow, but now I think I will spend some time looking at it in a little more detail and creating my own kernels etc.


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