MicroZed Chronicles: So what is Model based Engineering.

I have mentioned several times that I am a big fan of model based engineering especially for development of FPGA and embedded SoC. However, I think there is at times a little confusion over exactly what model based engineering actually is, with a lot of people thinking that model based engineering exclusively requires the use of tools such as Matlab / Simulink or Vitis Model Composer.

This is an incorrect view, while these tools can play a significant part in the model based engineering flow they are not explicitly required to follow a model based engineering approach.

So lets take a step back and understand what exactly a model based approach is and how we can use it in FPGA development. Regular readers will also know that along with model based engineering I am also a big advocate of system engineering.

Rather helpful model based engineering and system engineering, are actually the same thing in Model Based Systems Engineering.

The International Council on Systems Engineering (INCOSE) defines model based systems engineering as

“MBSE is the formalized application of modeling to support system requirements, design, analysis, verification and validation activities beginning in the conceptual design phase and continuing throughout development and later life cycle phases”

All of the things we need to do, to deliver successfully an FPGA design. MBSE moves us away from the document centric design flows, which often contain a lot of duplication to a model which acts as the single source of truth. Duplication is removed as the same piece of information can be reused in multiple places typically via linking.

To enable model based engineering, SysML (System Modelling Language) was developed, SysML provides a set of standards for the creation of diagram that can be used to describe the system as a diagrammatic based model.

These diagrams are generally created using a database of objects that are then used to create a set of SysML diagrams. The SysML diagrams are broadly divided into two groups; one group defines the structure of a system whilst the other describes the behaviour of a system.

Our approach to model based systems engineering is to leverages SysML, allowing us to define the system and the FPGA elements of that system. While at the same time being able to generate structural VHDL from the SysML Block Definition Diagram, with Internal Block Diagrams.

This enables us to easily link domains, concepts, requirements, preliminary design, sequences, and of course the physical FPGA structural. The MBSE approach therefore enables us to have a single source of truth we can share with the customer for reviews. This allows us to share concepts and sequences to ensure the flow is actually as intended, rather than presenting hundred of pages of documents. Although is we need to export to documents we can of course.

Lets take a look at a simple approach which used the block definition diagrams to define the physical FPGA architecture.   

The first diagram presents the block definition diagram which defines the elements of the physical FPGA. This includes not only the functionality but also the interfaces on the blocks and constituent blocks which sit at a lower level. While not shown in this example the it is possible to trace these IP blocks to requirements, or other assets for example state diagrams which define behaviour.

Delving into the internal block diagram are able to show the physical connections of the blocks in the FPGA. The connections between then are defined into interface classes enabling the correct RTL interfaces to be generated.

By creating new interface classes we are able to implement AXI, AXI Stream or custom interfaces between the modules. When the block diagram is generated this results in the correct interface style being implemented in the RTL. We wrote this to be tool independent so it currently uses all Adiuvo AXI Infrastructure including cross connects.

What these leaves us with then is a structural design, with requirements allocated to the modules. These modules can be then be developed using either traditional RTL, High Level Synthesis or Model Based tools like Simulink or Vitis Model Composer.

As such we are able to leverage model based engineering for applications from image and signal processing to developments such as PCIe interfaces, or SDI transmission for example. The skill as an engineer is in picking the most appropriate tool chain to deliver on time, quality and cost.

Our MBSE SysML flow is based around Sparx Systems Enterprise Architect which provides the front end for the diagram generation. A little Visual Basic and Python was then used to convert the diagram(s) into a VHDL representation.  The scripts also provide the internal register map and the interface control documentation for the project.

We find it works well and we have delivered several projects which use that approach across a mix of FPGA and MPSOC based solutions.

What is nice about this approach is that the model in enterprise architect remains the master, as such we are able to make changes and adjustments as needed and the regenerate the down stream components.

You might then be thinking how is this different to just drawing the architecture of using a graphical to HDL tool to generate the architecture. These are of course valid approaches however, using SysML, means we can link across requirements, and sequences etc to the block diagram. This provides for a better approach when working on projects which require traceability of requirements such as Space projects or D0254 based projects.

Of course tools like Simulink and Vitis Model Composer have a great impact on the development and enable the development at a higher level of abstraction, reducing time scales when appropriately used. However, they are not necessary to get started with a model based engineering flow.

If people are interested I will create project on Hackster demonstrating the flow.  

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