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MicroZed Chronicles: Seven Series BUFR and Clock Division

  • Mar 4
  • 4 min read

One of the most commonly implemented FPGA features is clock division. When dividing clocks there are several possible approaches depending upon the application. For simple integer division we can use counters implemented in logic, while more complex requirements such as frequency multiplication or fractional division typically require a PLL or MMCM.


Previously we explored clock division in 7-series devices using the BUFGCE, and in UltraScale devices using the BUFGCE_DIV. These structures allow clocks to be divided without consuming logic resources and without requiring a clock management tile.


However, one clocking resource we have not yet examined is the BUFR, which also provides clock division capabilities in 7-series devices.


Before we look at how the BUFR can be used, it is worth quickly recapping the 7-series clocking architecture.



Seven Series Clock Regions


Each 7-series FPGA is internally divided into several clock regions. Each clock region is typically 50 CLB rows high and contains dedicated clocking resources along with logic and specialised blocks such as IO, ISERDES, OSERDES, BRAM and DSP elements.


The global clock network, which we explored previously when looking at BUFG-based clock division, is capable of distributing clocks across all clock regions of the device. To support multi-clock designs, several global clock networks are provided.


These global clocks can originate from:


  • Clock-capable IO pins

  • Clock Management Tiles (MMCM or PLL)

  • Regional clock buffers

  • Fabric logic


Within each clock region there are also several regional clocking resources available:


BUFIO – An IO clock buffer used to clock high-speed IO logic. The BUFIO can drive IO structures such as ISERDES and OSERDES but cannot drive CLB logic. It is typically used in source-synchronous interfaces where the IO must operate at a higher frequency than the fabric logic.


BUFH – A horizontal clock buffer capable of driving a horizontal clock spine within a single clock region.


BUFR – A regional clock buffer capable of distributing a clock to resources across the entire clock region.


BUFR Clock Division


The BUFR provides a useful feature: it can divide the input clock by a factor between 1 and 8.


This capability is particularly useful for source-synchronous interfaces, where the IO may operate at a higher frequency while the fabric logic runs at a divided clock rate once the data has been de-serialised.


To explore this behaviour we can create a simple design that instantiates several BUFR primitives, each configured for a different division ratio.


When we simulate the design we can observe the output clocks generated for each division ratio.



The first and most obvious observation is that for even division ratios, the resulting clock has a 50:50 duty cycle.


For odd division ratios, however, the duty cycle is not perfectly symmetrical. One half of the clock period contains one additional input clock cycle, resulting in a slightly asymmetric duty cycle.


BUFR Bypass Mode


Another important aspect of the BUFR is the BYPASS mode.


At first glance this might appear equivalent to configuring the divider for divide-by-1, however the behaviour is slightly different.


When the BUFR is configured in BYPASS mode, the divider is skipped entirely and the CE (clock enable) and CLR (clear) controls are ignored. In this mode the BUFR behaves as a simple regional clock buffer.


When configured for divide-by-1, the clock is not divided but the CE and CLR controls remain active.


Because the divider logic is bypassed entirely in BYPASS mode, the clock path has slightly lower latency. While the difference is small, it can be important when working with high-speed interfaces.


Distributing a BUFR Clock


Although the BUFR drives the regional clock network, it is possible to forward the BUFR output into a global buffer (BUFG) if the clock needs to be distributed across the entire device.


This allows the divided clock to be used beyond the local clock region if required.


Final Thoughts


The BUFR is a useful and often overlooked clocking resource within 7-series devices. Its built-in clock division capability provides a simple and efficient way to generate lower-frequency clocks within a clock region without consuming fabric resources or using an MMCM or PLL.


As always, the example code for this article is available on my GitHub if you would like to explore it further.


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