One of the most commonly implemented FPGA features is clock division. When dividing clocks there are several possible approaches depending upon the application. For simple integer division we can use counters implemented in logic, while more complex requirements such as frequency multiplication or fractional division typically require a PLL or MMCM. Previously we explored clock division in 7-series devices using the BUFGCE, and in UltraScale devices using the BUFGCE_DIV. Thes