MicroZed Chronicles: Keep It Simple Stupid and Lessons from It

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Last week, I had the pleasure of presenting the keynote at the CERN FPGA Developers Forum in Geneva. While talking with other attendees, I got into a discussion with Alen Luin, and during our conversation about FPGAs, the importance of the KISS principle in FPGA design came up.

The KISS principle is one that we should keep in mind as we architect our systems and FPGA designs. Anyone can create a complex solution; the best engineers can implement complex requirements in a simple manner.

However, beyond the overall KISS principle, there are several adaptations we can leverage to help us design better FPGAs. Alen and I spent about 20 minutes discussing and identifying them.

Keep It Simple Stupid

When developing the architecture, use the simplest solution possible. Leverage IP blocks and reuse modules from previous developments wherever practical. Use hierarchy effectively and ensure the architecture aligns with methodologies such as the UltraFast Design Methodology.

Keep Information Simple Stupid

Ensure the module or design is properly documented. This documentation should provide descriptions of functional behaviour, register address spaces, interfaces, expected behaviour under fault or error conditions, and a simple architectural model of the design. Leverage tools such as WaveDrom and bitfield whenever possible to create clear and concise documentation.

Keep It Synchronous Stupid

Your design should be synchronous: register everything and avoid latches. When working with high-performance designs, do not forget to include pipeline registers, which can be redistributed throughout the design to help achieve timing closure.

Keep Clocking Simple Stupid

Minimise the number of clock domains within a design wherever possible. Every additional clock domain introduces complexity through clock domain crossings (CDCs), increased verification effort, and more challenging timing constraints. Use clock enables instead of generating additional clocks in logic, and leverage dedicated clocking resources such as MMCMs and PLLs.

When clock domain crossing is required, make sure you leverage the Xilinx Parameterized Macros (XPMs) and ensure CDC analysis is performed correctly, as CDC issues can be very difficult to identify in simulation.

Keep Inference Simple Stupid

We want to develop RTL that is both portable and flexible. When working with FPGA resources such as BRAMs and DSP blocks, it is often best to leverage inference. Write your code in such a way that the synthesis tool can infer the correct primitive, whether that be a BRAM, DSP, or other FPGA resource. This makes the code more portable between device families, for example, moving from DSP48 to DSP58 architectures.

There are occasions where explicit instantiation is necessary to access device-specific features or achieve the required performance. When this is the case, ensure the instantiated primitive is contained within its own module, making future replacement or migration easier.

Keep Interfaces Standard Stupid

Effective designs use standardised interfaces. This enables easy interaction between modules and facilitates the reuse of existing designs. When developing RTL at Adiuvo, we leverage AXI, AXI Lite, and AXI Stream interfaces. These interfaces are straightforward to implement and enable designs to scale from simple memory-mapped register access, through high-performance memory-mapped data transfer, to unidirectional streaming applications.

Keep It Scalable Stupid

As mentioned before, and several times throughout this blog, I am very keen on design reuse. One of the key enablers of design reuse, alongside standard interfaces, is the use of generics and generate statements in VHDL, or parameters in Verilog, to create modules that can be adapted for different use cases.

This prevents the need for copy-and-paste development and allows us to be more efficient in our FPGA developments, which is critical when delivering projects on time, to the required quality, and within budget.

Keep Initialisation Simple Stupid

When trying to achieve timing closure, control sets can have a significant impact on Vivado's ability to meet timing. Control sets include clock enables and set/reset signals. These control sets consume not only logic resources but also routing resources and increase implementation complexity, as all registers within a slice must share the same control set.

When targeting AMD FPGAs, it is often better to rely on the Global Set/Reset (GSR) provided during configuration, favouring signal initialisation over complex reset trees. This is not to say that resets are never required, but as engineers we should strive to minimise reset-tree fan-out wherever possible.

Keep Verification Simple Stupid

Leverage standard verification frameworks such as UVVM, OSVVM, Cocotb, and UVM. Architect modules with clear interfaces and deterministic behaviour to simplify both simulation and hardware debugging.

Ensure you have a defined set of test cases that are implemented within the testbench to verify the module thoroughly. Designs that are easy to verify are often easier to maintain and extend.

While this is a somewhat whimsical blog, it provides an easy way to remember several key tenets of FPGA design, all based on a commonly used engineering term.

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