top of page

MicroZed Chronicles: Power Design Manager

Designing a successful system requires not only the implementation of the algorithms within the programmable logic and processing systems offered by AMD FPGA and System on Chips, but also ensuring the design of the hardware is correct. One major aspect of this is determining the power required by the device.


Developing electronic solutions from scratch is a complex endeavour, normally the starting point is customer requirements, which are then expanded upon to create a set of requirements for the electronic design. There will also be a set of requirements for the functionality of the FPGA / SoC of course.


One of the more challenging aspects of the requirements will be the power budget. The power budget defines the allocation of the available power to the different elements of the system. For many applications this power budget is constrained, this makes accurate power budgets and estimation early on in a project very important.


Accurate predictions will reduce technical risk associated with the power budget, along with enabling the power system implemented to be correctly scaled. One method of achieving an accurate power estimate is to use Xilinx Power Estimator (XPE) for 7, UltraScale and UltraScale+ series. We could use XPE to estimate and scope the power requirements, then later validate in Vivado.


Recently, we’ve been working on several Kria-based designs. Developing the power estimate for the Kria SoM and carrier card is one of the earliest things we do to ensure it algins with the power budget. This is where it gets interesting as AMD has introduced for both Versal and Kria a new power design manager tool which is used to estimate the power and thermal loading.


To get started with this tool the first stage is to download and install it from the AMD downloads page. If you still have the installer downloaded from installing 2023.1 you can also use that as the unified installer is used.


Once PDM is installed we can open the application and create a new project, in this case we will look at Kria (we will look at Versal in another blog).



With the project open we can select the type of Kria we are working with, the SoM itself or the KV260 board. We can also select the grade and the process we wish to work with. At early stages of development I always prefer to work with the maximum process.


To get started determining the power estimate, we can start with the PS and VCU configuration. Here we are presented with a very comprehensive dialog which allows us to configure the PS and the VCU.

Using this dialog we are able to configure the PS, the PS, PL interfaces used and estimate the loading on those interfaces.


With the PS configured the next step is to determine the clocking used in the PL, rather helpfully we can also create clocks in PDM.

These clocks definitions are very comprehensive as they enable the clock name and any clock manager and sub clocks to be entered.

The following tabs enable us to configure the logic, BRAM, URAM and DSP elements needed in the programable logic design.

The final stage is to define the IO which will be used on the system, this includes both the PS MIO and the PL.

Here we can set the VCCIO, the interfacing of the system and even the GTR, GTH utilisation and power.


One of the nice things about working with the Kria SoM in PDM, is it is aware of the power architecture on the SoM module. As such it will inform you if the power estimate is beyond what the power devices on the SoM can supply.


This provides a nice approach to estimating our Kria power dissipation, we will come back to this and look at it for Versal soon.


Workshops and Webinars


If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include

Embedded System Book Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here. Order here

0 comments

Comments


bottom of page