as we develop programmable logic-based solutions. We have two choices when doing this, either create a full IP XACT IP or just add the HDL to the IP Integrator block diagram.
Creating a complete IP-XACT definition and including it into the Vivado library, is the path we should follow if we want to create a reuseable and portable library of components. There are, however, instances where we want to create a simple HDL module for inclusion within the IP Integrator block diagram. In this blog, we are going to discuss how we can effectively implement this HDL approach.
To get started, we need to create the HDL files. I am going to use the HDL files created for my Hackster project which enabled a UART (provided by a RPI Pico) to access the AXI network within a FPGA design.
This is a good example because it allows us to have several different interface types within our HDL. The first thing I did was to create a new Vivado project targeting an Arty A7 development board. With the project created, the next step is to create a block diagram and add in the three files downloaded from the Hackster project.
Once the files have been added to the project, we can drag and drop them from the source tab onto the block diagram. Since I paid special attention to include AXIS or AXI within the signal name when I wrote the VHDL for the AXI and AXIS interfaces, Vivado is quickly and easily able to work out that the HDL blocks contained these AXI-based interfaces.
However, if we had used different signal names or an alternate naming convention, this could mean that Vivado is not able to automatically detect the interface. A naming convention, for example, which complies with company naming standards often defines certain rules on names such as pre or post fixes. This might not be an issue for small modules and designs but as your design gets larger it becomes challenging to ensure clarity when several tens of signals are criss crossing the design.
This is where we are able to use attributes defined in our HDL code to help Vivado understand the interface for IP Integrator.
The list of interfaces supported is comprehensive and can be accessed using Vivado’s language templates. Select the language you desire (VHDL or Verilog) and you will see several examples of the interfaces supported under IP Integrator HDL. Along with these interfaces, there are attributes which can be put in the HDL to ensure Vivado is able to detect the interface type.
You’ll notice in our example above, Vivado detected the AXI interfaces but did not detect the UART interface. If we wish to ensure that this simple interface is detected, we can add the attributes within the file uart.vhd.
ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO of rx: SIGNAL is "xilinx.com:interface:uart:1.0 uart RxD"; ATTRIBUTE X_INTERFACE_INFO of tx: SIGNAL is "xilinx.com:interface:uart:1.0 uart TxD";With the attributes added, referenced modules within the IP Integrator block diagrams will be out of date and need to be refreshed. After the modules have been refreshed, you will see a new UART port on the UART module.
We can also use these attributes to define clocking, and reset and interrupt information for the HDL modules.
As we have seen in this blog, there is a wide range of interfaces supported from simple UART to video timing, S/R/GMii, PCIe and more.
Using these attributes ensures that our IP Integrator block diagrams are clear and concise which helps us during the design and also when we come back to projects at a later point in time
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