MicroZed Chronicles: How I Am Using AI

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Recently, we have looked at how we can use AI in our RTL development and in our software development within Vitis. AMD is also going to be running a very interesting tutorial on upcoming AI features within FPGA at FPGA Horizons US.

This got me thinking that I should write a little more about how I am using it and the flow I am using in my developments.

The first question is: what am I using it for? I am mostly using it for simple tasks such as creating IP core interfaces in the PL, or generating software which can configure the PL when working with bare-metal applications.

I am not throwing entire solutions at it and asking it to create a complete design. You might be able to do that higher up the stack, but when you need to understand not only the logic design, but also pin placement, constraints, and the actual hardware it will run on, it is not yet capable and will quickly end in pain.

For this blog, let’s focus on PL developments. The frame of reference I want to use is IP cores. We often use them in our Vivado designs, and they are great because they enable us to develop our applications much quicker and more easily than having to write everything from scratch.

However, there does not always exist an IP core which provides the function we require. This is one of the areas in which I use AI to assist.

As we have talked about previously, my RTL development environment is VS Code with Co-pilot enabled as an agent. When it comes to models, I typically use Claude Opus 4.5 or 4.6, depending on the application.

A real example of this is on my Spartan-7 embedded system tile. I have a PSRAM connected to the device, for which I wanted to create an IP core. I wanted a module that presents an AXI memory-mapped interface to the logic, and the PSRAM interface externally, enabling reads and writes.

To develop this using AI, the first thing I did was create a directory which contained several references for the AI. These are not related specifically to the project, but include several key things it needs to know for every project I ask of it.

These include:

• Adiuvo RTL Coding Guidelines: guidelines for how RTL should be developed by Adiuvo employees, contractors, and now agents

• AMD Ultrafast Design Methodology Guidelines: guidelines on how to develop RTL solutions for AMD FPGAs

• Adiuvo IP Rules: rules on how IP should be developed, documented, and stored, for example directory structure

• Adiuvo IP Libraries: locations of the Adiuvo IP repositories so the agent can leverage them if necessary

  
  

Within the working folder of the development, I also create an instructions document which defines what I want the agent to achieve. Typically, this includes the functionality, links to datasheets and schematics, and what I want for verification, including test benches and trial synthesis or project implementation. Depending on the complexity of the IP core I wish to create, this can be simple or more detailed.

When it comes to AXI interfaces I often ask for the AXI Verification IP to be used in the test benches.

Often, I want to be able to connect to hardware in the loop and test. In this instance, I asked the agent to connect the created IP core to an AXI-to-JTAG interface and create a Python script which would debug the IP core and attached memory from the development machine.

To accept the generated code, I typically do the following:

1. Review the RTL myself to ensure it looks as I would expect

2. Review the test bench to ensure it tests the corner cases and boundary conditions I expect. I also ensure the tests are sensible. For more complex developments, it is a good idea to generate a number of test cases and expected results in your instructions using CSV, etc.

3. Examine the resource utilisation of the implementation to ensure it aligns with my expectations and experience

4. Run a static analysis tool on the produced RTL to ensure it complies with our RTL coding standards and Ultrafast design rules. I recently wrote about how I did this, with examples, in a white paper

   
   

All of these points are where your experience of FPGA development comes into its own. Honestly, it is similar to what you would do if another team member, especially a more junior one, developed the module.

Now, a couple of important points. As the cloud is involved and this is not being developed on locally hosted machines, I do not do anything which is commercially or client sensitive using AI.

One thing is for sure: AI is going to be part of FPGA development going forward. It is just another level of abstraction and part of the journey, following the progression from Boolean equations to schematic entry, to RTLs, and now to AI-assisted development.

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