MicroZed Chronicles: FPGA Horizons US

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here.

The $99 Artix UltraScale+ Explorer Board - learn more here

I am not going to lie, I was a little nervous in the run up to FPGA Horizons US. It is one thing to organise a conference in London just down the road from me. It is another thing entirely to organise one 3,000 miles away.

Having spent the last few days there, I can confirm there was no need to be. It was an amazing event which brought together FPGA engineers and the electronic engineers attending PCB East, our partner conference.

Over two days, 200-plus FPGA engineers attended over 20 talks and a day-long hands-on workshop. We have made all of the slides available on the FPGA Horizons US web page (some are still in the approval process and will appear over the next few days) but let's take a look at some of my favourite talks from the event.

The event kicked off with a keynote from Martin Charron at AMD. Martin provided a wonderful overview of AMD's history, looking at the devices and tools that have brought us to modern FPGA and SoC development. He then outlined where programmable logic and tools were headed, which was a nice set-up for day two's hands-on lab on agentic workflows for modern SoCs.

From the keynote, two parallel tracks ran, consisting of focused 20-minute talks alongside longer panels and tutorials.

One of my favourite sessions was An Introduction to SI for the FPGA/SoC Designer by Matt Burns at Samtec. Over an hour, Matt walked attendees through the signal integrity channel, the components of a signal, and the importance of matching and insertion losses. A solid introduction to signal integrity and why it matters. (slides)

On verification, Jim Lewis presented on how OSVVM can accelerate the development of better testbenches (slides), while Aldec presented on the power of static analysis to ensure higher quality HDL code, reinforcing the well-worn lesson that catching issues earlier is much cheaper in terms of both development time and financial cost. (slides)

Continuing the verification theme, Jamie Tidman from certiqo.ai talked about the development of an AI verification project funded by the European Space Agency, which is capable of examining requirements against RTL to highlight any implementation issues that might be present.

The idea is that, prior to simulation and formal verification, the tool can identify areas which may not fully implement the desired functionality, along with requirements which have no implementation at all. It can also identify code which does not trace back to any requirement, which is useful for security audits, particularly when LLMs have been used in RTL generation. (slides)

Security featured in several talks. Ted Speers at Microchip presented a journey through FPGA security (slides), Xiphera presented a common framework for a hardware root of trust, and Shahin Tajik from WPI talked about securing FPGAs against advanced physical attacks.

Several talks touched on AI. I spoke about how I had used AI to help me recreate the F-14 CADC. A fun story, but the underlying message was that we can use LLMs to help us understand legacy designs where the documentation is not what we might expect in the modern day.

Altera presented on how developers can leverage the FPGA AI Suite to implement AI-based designs in FPGAs, while both Lattice and Efinix presented on image processing techniques and applications, which form the core of many AI and computer vision systems.

Taken together, the AI thread running through the event was striking. From legacy reverse engineering, to verification, to inference acceleration, and on to vision pipelines, AI is now a recurring presence across the FPGA flow rather than a niche topic confined to a single track.

All told, it was an excellent conference. The next is in London in October 2026, and we will be returning for FPGA Horizons US '27. Hope to see you there.

FPGA Conference

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here.

FPGA Journal

Read about cutting edge FPGA developments, in the FPGA Horizons Journal or contribute an article.

Workshops and Webinars:

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include:

• Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal

• Professional PYNQ Learn how to use PYNQ in your developments

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• Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux

• Arty Z7-20 Class looking at HW, SW and PetaLinux

• Mastering MicroBlaze  learn how to create MicroBlaze solutions

• HLS Hero Workshop  learn how to create High Level Synthesis based solutions

• Perfecting Petalinux  learn how to create and work with PetaLinux OS

Boards

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• Adiuvo Embedded System Development board - Embedded System Development Board

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• SpaceWire RMAP Initiator - SpaceWire RMAP Initiator,  digital download, AXIS & AXI4 Interfaces

• SpaceWire RMAP Target - SpaceWire Target, digital download, AXI4 and AXIS Interfaces

• Other Adiuvo Boards & Projects.

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Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here.  Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.

All words in this blog were written by a human.