MicroZed Chronicles: Introducing the Explorer Board

FPGA Conferences

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here.

This week marks two milestones I have been looking forward to for some time: the opening of FPGA Horizons US, and the launch of a new Adiuvo development board, the Explorer Board.

The Explorer is the first Adiuvo board built around an Artix UltraScale+ device, and I think it fills a gap in the market that has been bothering me for a while. The Explorer changes that. Our target price is $99.

The silicon

At the heart of the Explorer is the Artix UltraScale+ AU7P in the FCVA289 package. For readers who have not looked at the AU7P before, it offers 37K LUTs, 75K flip-flops, 216 DSP slices, 3.6 Mb of Block RAM, and four GTH transceivers. That is a genuinely capable device for signal processing, embedded acceleration, and communications work, and it is the smallest member of a family that scales up considerably if a design later needs to grow.

Crucially, the AU7P supports the MicroBlaze V soft processor, which is where a lot of my own interest sits. To support embedded operating systems and more demanding MicroBlaze V applications, we have included a HyperRAM on the board. That combination of UltraScale+ fabric, MicroBlaze V, and external memory makes the Explorer a very flexible platform for embedded and DSP experimentation.

Getting the I/O out

One of the more interesting engineering stories on this board is how we have dealt with the FCVA289 package itself. At a 0.5 mm pitch, conventional wisdom says you need High Density Interconnect (HDI) technology to break the device out, and HDI adds significant cost to the PCB. For a board we want to land at $99, that was a non-starter.

Instead, we have used an Offset Through-Hole Via (OTHV) strategy, which allows the device to break out on a conventional stack-up without HDI. It is a nice example of a layout technique pulling cost out of a design without compromising the electrical performance, and it is one of the reasons we can hit the price point we have set.

Interfaces

To make sure users can actually exercise the logic and transceiver resources, the Explorer provides:

• Four Pmod interfaces for sensors, displays, and general-purpose peripherals

• Two HSIO interfaces, one for high-speed LVDS differential signalling, and one that breaks out the GTH transceivers

• Compatibility with selected Zmod and SYZYGY modules, including the Zmod Scope, Digitizer, and AWG

The HSIO interfaces are the headline feature for anyone wanting to do real signal processing or high-speed I/O work. Pair the Explorer with a Zmod Scope or Digitizer and you have a serious little instrumentation platform.

There are, of course, the usual LEDs and push-buttons for basic indication and interfacing.

Power and monitoring

The Explorer runs from a single USB-C connection, which keeps the desk clean. We have also broken out access to the on-board power supplies so users can accurately measure the power drawn by the algorithms they are developing. This is something I have wanted on a low-cost board for a long time, especially for teaching. If you are going to talk to students about DSP efficiency or power-aware design, you really do need to be able to measure what the device is actually consuming.

Open by default

In keeping with Adiuvo's values, once layout is complete the schematics, BOM, and PCB layout will all be released open source.

Where next

The plan is to have production boards running Labs at FPGA Horizons UK in October, and I will be writing up reference designs, MicroBlaze V tutorials, and signal processing examples here in the MicroZed Chronicles as the board comes online.

If the Explorer sounds like something you would find useful, whether for professional prototyping, teaching, or just to get your hands on an Artix UltraScale+ device please register your interest at explorerboard.tech. It genuinely helps us plan the first production run.

FPGA Conference

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here.

FPGA Journal

Read about cutting edge FPGA developments, in the FPGA Horizons Journal or contribute an article.

Workshops and Webinars:

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include:

• Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal

• Professional PYNQ Learn how to use PYNQ in your developments

• Introduction to Vivado learn how to use AMD Vivado

• Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux

• Arty Z7-20 Class looking at HW, SW and PetaLinux

• Mastering MicroBlaze  learn how to create MicroBlaze solutions

• HLS Hero Workshop  learn how to create High Level Synthesis based solutions

• Perfecting Petalinux  learn how to create and work with PetaLinux OS

Boards

Get an Adiuvo development board:

• Adiuvo Embedded System Development board - Embedded System Development Board

• Adiuvo Embedded System Tile - Low Risk way to add a FPGA to your design.

• SpaceWire CODEC - SpaceWire CODEC, digital download, AXIS Interfaces

• SpaceWire RMAP Initiator - SpaceWire RMAP Initiator,  digital download, AXIS & AXI4 Interfaces

• SpaceWire RMAP Target - SpaceWire Target, digital download, AXI4 and AXIS Interfaces

• Other Adiuvo Boards & Projects.

Embedded System Book   

Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here.  Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.

All words in this blog were written by a human.