MicroZed Chronicles: Explorer’s First Application

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The $99 Artix UltraScale+ Explorer Board - learn more here

Over the last few weeks, whenever I have had some spare time, I have been bringing up the Explorer board. So far, most of the board is up and running, and the signal integrity measurements appear to be aligning with our expectations. I will talk more about this later once we have completed our analysis.

However, one of the things I have wanted to do for a while is create the first example application and showcase some of the board’s capabilities. Of course, we have the Artix UltraScale+ FPGA, which provides phenomenal performance, but we also have IO such as Pmod, HSIO, SYZYGY interfaces and transceivers, along with the system controller running on the RP2040.

The RP2040 system controller enables the Explorer board to adjust IO voltages for the HSIO and SYZYGY interfaces. It also monitors the PMIC voltages and status, and can measure internal FPGA parameters thanks to I²C access to the System Monitor in the AUP.

Access to the RP2040 and the application running on it is available over USB-C, meaning that we can access and control most of the board’s systems. Now, a word of warning: with great power comes great responsibility. If you do not know what you are doing, you can damage the board, as it provides direct access to the PMIC.

For the demo project, I wanted to create something that would showcase the Pmod IO and the power of the AUP device. As such, I decided to adapt the SCU35 environmental monitoring reference design that I created previously.

For the time being, I replaced Ethernet with a USB serial port, although we do have an Ethernet Pmod coming for the Explorer board.

Across the four Pmod ports on the Explorer board, we have Hygro, RTC, TC1 and ALS Pmods. The data collected by the sensors is time-tagged by the RTC and sent over UART to a host, where it can be plotted.

The hardware design is very simple. We can instantiate a MicroBlaze V processor and connect the Pmod drivers from the Digilent Vivado library. I did have to customise the IP to support AUP devices.

You can see the System Monitor sitting in isolation at the bottom of the design. This connection to the RP2040 enables the AUP FPGA to be protected if the temperature gets too high or the voltages go out of range, for example.

The implementation figures are good. They show that, with the MicroBlaze V instantiated, we are using around 10% of the logic resources. This gives us plenty of room for more interesting processing and applications as we develop further demos for this board and explore its capabilities.

The software is straightforward to write. We just need to initialise the Pmods correctly and then cycle around sending their values over UART.

Running a Python application on the host computer shows the results below. We can see the values reported by the board, and by covering, heating or cooling the sensors, we can see a reaction.

Of course, this project is for the Explorer board, which is as yet unreleased. However, the same project can easily be ported to one of the Arty families in the meantime. It is important, though, as it shows that the Explorer board is taking shape.

We can now be happy with the Pmod interface, the FPGA and its configuration memories, the power and clocking architecture, and of course, the system controller is working as intended.

Next up is the verification of the higher-speed interfaces and transceiver interfaces. These are the features that set this board into a class of its own.

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