MicroZed Chronicles: Embedded Plus+ Architecture.

One thing which has been interesting to me since I first came across it was the embedded+ architecture. Developed by Sapphire Technology the embedded plus architecture, combines a AMD x86 Ryzen R2314 with a AMD Versal 2302, within a mini ITX form factor.

The primary communication channel between the Ryzen processor and the Versal SoC is the PCIe which can be configured to support from x1 offering a single lane to x16 with 16 lanes providing for maximum transfer bandwidths. In this configuration the Ryzen is configured as the PCIe root port and Versal 2302 as the PCIe End point.

The embedded+ provides developers with the ability to leverage high performance application software running on the Ryzen using a OS such a Linux. While the Versal 2302 provides the ability for hard real time, deterministic and accelerated applications. This allows the application running on the Ryzen to be able to access and work with not only the programmable logic within the 2302 but also the AI engines and the hardware peripherals within the 2302 including the transceivers, MIPI and 40G Ethernet cores. As we will see the programmable logic IO is also useful in this application for creating any to any interfacing of the FPGA.

First lets talk about the processor which is not something we have discussed much being primarily focused on FPGA and SoC development. The Ryzen Embedded R2314 contains four cores capable of supporting 4 threads, operates at a base 2.1GHz, with a boost capability of up to 3.5 GHz. When it comes to multimedia the Ryzen processor also includes Radeon graphics meaning it is capable of supporting up to three 4K displays. To support the host application 64GB of DDR4 memory is connected to the Ryzen R2314. As the Ryzen is designed for the edge, power efficiency is critical as such its maximum power dissipation is 35W.

When it comes to interfacing with the Embedded+ the Ryzen provides support for traditional embedded interfaces such as Ethernet, USB, HDMI, Audio and Serial communications. While the Versal SoM provides an expansion connector which enables the versal IO to be leveraged for a range of different applications. Using this expansion connector we could interface with further sensors such as Cameras, LIDAR, or sensors of other modalities. We can also use the expansion port to include different communication interfaces, such as Ethernet, or legacy / bespoke interfaces.

The development of the Versal application has two development flows, the traditional flow with the application developed using Vivado intended for those engineers more familiar with FPGA development. While a Vitis Flow enables developers to leverage the system development flow to leverage a higher level development approach. Key elements of the Vitis flow include the XRT Run time and the Versal Management Runtime. Elements of the XRT execute on the Versal 2302 and the x86 Ryzen to be able to provide application execution and management of the Versal device.

As for debug of the Versal 2302 we can connect externally over a USB JTAG as normal, alternatively we are able to connect the USB JTAG via a switch to the Ryzen processor which enables the Ryzen to perform debugging.

Over the next few weeks I am going to explore this architecture a little more and create my first application. I am looking forward to learning more about the Embedded+ architecture and what we are able to do with it.

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